| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -1/+1 | |
| | | ||||||
| * | Connections between inputs and inouts are driven by the input | Clifford Wolf | 2016-04-26 | 1 | -0/+3 | |
| | | ||||||
| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 1 | -1/+1 | |
| | | ||||||
| * | Use alphanumerical order instead of idstring idx in opt_clean compare_signals() | Clifford Wolf | 2016-02-02 | 1 | -1/+1 | |
| | | ||||||
| * | Fixed opt_clean handling of inout ports | Clifford Wolf | 2015-08-16 | 1 | -2/+2 | |
| | | ||||||
| * | Improved handling of "keep" attributes in hierarchical designs in opt_clean | Clifford Wolf | 2015-08-12 | 1 | -25/+57 | |
| | | ||||||
| * | Merge pull request #70 from gaomy3832/bugfix | Clifford Wolf | 2015-08-12 | 1 | -0/+10 | |
| |\ | | | | | Remove unused blackbox modules in opt_clean. | |||||
| | * | Remove unused blackbox modules in opt_clean. | Mingyu Gao | 2015-08-11 | 1 | -0/+10 | |
| | | | ||||||
| * | | Added missing ct_all setup to opt_clean | Clifford Wolf | 2015-08-11 | 1 | -0/+3 | |
| |/ | ||||||
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -5/+5 | |
| | | ||||||
| * | preserve used $-wires with init attribute in opt_clean | Clifford Wolf | 2015-05-22 | 1 | -1/+1 | |
| | | ||||||
| * | Added non-std verilog assume() statement | Clifford Wolf | 2015-02-26 | 1 | -1/+1 | |
| | | ||||||
| * | Some cleanups in "clean" | Clifford Wolf | 2015-02-24 | 1 | -7/+14 | |
| | | ||||||
| * | Added $meminit cell type | Clifford Wolf | 2015-02-14 | 1 | -1/+1 | |
| | | ||||||
| * | Fixed opt_clean performance bug | Clifford Wolf | 2015-02-04 | 1 | -26/+26 | |
| | | ||||||
| * | Using design->selected_modules() in opt_* | Clifford Wolf | 2015-02-03 | 1 | -16/+10 | |
| | | ||||||
| * | Added dict/pool.sort() | Clifford Wolf | 2015-01-24 | 1 | -0/+4 | |
| | | ||||||
| * | Cleanups in opt_clean | Clifford Wolf | 2014-12-29 | 1 | -10/+10 | |
| | | ||||||
| * | dict/pool changes in opt_clean | Clifford Wolf | 2014-12-29 | 1 | -5/+5 | |
| | | ||||||
| * | Renamed hashmap.h to hashlib.h, some related improvements | Clifford Wolf | 2014-12-28 | 1 | -1/+1 | |
| | | ||||||
| * | More hashtable finetuning | Clifford Wolf | 2014-12-27 | 1 | -1/+1 | |
| | | ||||||
| * | Replaced std::unordered_set (nodict) with Yosys::pool | Clifford Wolf | 2014-12-26 | 1 | -1/+1 | |
| | | ||||||
| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -1/+1 | |
| | | ||||||
| * | Fixed various VS warnings | Clifford Wolf | 2014-10-18 | 1 | -1/+1 | |
| | | ||||||
| * | Some cleanups in opt_clean | Clifford Wolf | 2014-10-16 | 1 | -16/+9 | |
| | | ||||||
| * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 1 | -4/+4 | |
| | | ||||||
| * | Added $_BUF_ cell type | Clifford Wolf | 2014-10-03 | 1 | -2/+2 | |
| | | ||||||
| * | remove buffers in opt_clean | Clifford Wolf | 2014-10-03 | 1 | -0/+13 | |
| | | ||||||
| * | Added support for "keep" on modules | Clifford Wolf | 2014-09-29 | 1 | -1/+1 | |
| | | ||||||
| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -8/+12 | |
| | | ||||||
| * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 1 | -2/+2 | |
| | | ||||||
| * | Added design->scratchpad | Clifford Wolf | 2014-08-30 | 1 | -4/+3 | |
| | | ||||||
| * | More idstring sort_by_* helpers and fixed tpl ordering in techmap | Clifford Wolf | 2014-08-15 | 1 | -2/+2 | |
| | | ||||||
| * | More cleanups related to RTLIL::IdString usage | Clifford Wolf | 2014-08-02 | 1 | -3/+4 | |
| | | ||||||
| * | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 | 1 | -2/+1 | |
| | | ||||||
| * | Added SigPool::check(bit) | Clifford Wolf | 2014-07-27 | 1 | -2/+2 | |
| | | ||||||
| * | Fixed bug in opt_clean | Clifford Wolf | 2014-07-27 | 1 | -1/+1 | |
| | | ||||||
| * | Fixed a bug in opt_clean and some RTLIL API usage cleanups | Clifford Wolf | 2014-07-27 | 1 | -3/+4 | |
| | | ||||||
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -2/+2 | |
| | | ||||||
| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -4/+4 | |
| | | ||||||
| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -5/+5 | |
| | | ||||||
| * | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -6/+10 | |
| | | ||||||
| * | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 1 | -2/+2 | |
| | | ||||||
| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -8/+8 | |
| | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | |||||
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -8/+8 | |
| | | ||||||
| * | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 1 | -2/+1 | |
| | | ||||||
| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 1 | -9/+4 | |
| | | ||||||
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 | 1 | -2/+0 | |
| | | ||||||
| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 1 | -10/+7 | |
| | | ||||||
| * | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 | 1 | -1/+1 | |
| | | ||||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |