| Commit message (Expand) | Author | Age | Files | Lines |
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| * | | Merge pull request #773 from whitequark/opt_lut_elim_fixes | Clifford Wolf | 2019-01-02 | 1 | -8/+31 |
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| | * | | opt_lut: reflect changes in sigmap. | whitequark | 2019-01-02 | 1 | -0/+2 |
| | * | | opt_lut: use a worklist, and revisit cells affected by elimination. | whitequark | 2019-01-02 | 1 | -3/+10 |
| | * | | opt_lut: count eliminated cells, and set opt.did_something for them. | whitequark | 2019-01-02 | 1 | -6/+20 |
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| * / | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 2 | -2/+2 |
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| * | opt_lut: eliminate LUTs evaluating to constants or inputs. | whitequark | 2018-12-31 | 1 | -0/+81 |
| * | Fix handling of (* keep *) wires in wreduce | Clifford Wolf | 2018-12-31 | 1 | -1/+4 |
| * | Merge pull request #720 from whitequark/master | Clifford Wolf | 2018-12-16 | 1 | -1/+1 |
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| | * | opt_lut: simplify type conversion. NFC. | whitequark | 2018-12-05 | 1 | -1/+1 |
| * | | opt_lut: leave intact LUTs with cascade feeding module outputs. | whitequark | 2018-12-07 | 1 | -0/+6 |
| * | | opt_lut: show original truth table for both cells. | whitequark | 2018-12-07 | 1 | -2/+3 |
| * | | opt_lut: add -limit option, for debugging misoptimizations. | whitequark | 2018-12-07 | 1 | -3/+21 |
| * | | Bugfix in opt_expr handling of a<0 and a>=0 | Clifford Wolf | 2018-12-06 | 1 | -1/+1 |
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| * | Rename opt_lut.cpp to opt_lut.cc | Clifford Wolf | 2018-12-05 | 1 | -0/+0 |
| * | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. | whitequark | 2018-12-05 | 1 | -17/+163 |
| * | opt_lut: always prefer to eliminate 1-LUTs. | whitequark | 2018-12-05 | 1 | -19/+41 |
| * | opt_lut: collect and display statistics. | whitequark | 2018-12-05 | 1 | -4/+33 |
| * | opt_lut: refactor to use a worker. NFC. | whitequark | 2018-12-05 | 1 | -170/+177 |
| * | opt_lut: new pass, to combine LUTs for tighter packing. | whitequark | 2018-12-05 | 2 | -0/+275 |
| * | Add iteration limit to "opt_muxtree" | Clifford Wolf | 2018-11-20 | 1 | -1/+17 |
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 11 | -24/+24 |
| * | Add optimization of tristate buffer with constant control input | Clifford Wolf | 2018-05-12 | 1 | -0/+17 |
| * | Fix opt_rmdff handling of $dlatchsr | Clifford Wolf | 2018-02-26 | 1 | -0/+3 |
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -0/+2 |
| * | Add warnings for driver-driver conflicts between FFs (and other cells) and co... | Clifford Wolf | 2017-12-12 | 1 | -1/+8 |
| * | Fix memory corruption bug in opt_rmdff | Clifford Wolf | 2017-10-26 | 1 | -0/+3 |
| * | Fix typo in opt_clean log message | Clifford Wolf | 2017-10-26 | 1 | -1/+1 |
| * | Revert 90be0d8 as it causes endless loops for some designs | Clifford Wolf | 2017-10-14 | 1 | -1/+0 |
| * | Fix input vector for reduce cells. | Kaj Tuomi | 2017-10-12 | 1 | -0/+1 |
| * | Minor changes to opt_demorgan requested during code review | Andrew Zonenberg | 2017-09-14 | 2 | -18/+18 |
| * | Initial version of opt_demorgan is functioning for AND/OR gates. Not the pret... | Andrew Zonenberg | 2017-09-12 | 2 | -0/+203 |
| * | Don't track , ... contradictions through x/z-bits | Clifford Wolf | 2017-08-25 | 1 | -1/+4 |
| * | Add removing of redundant pairs of bits in ==, ===, !=, and !== to opt_expr | Clifford Wolf | 2017-08-25 | 1 | -0/+72 |
| * | Mostly coding style related fixes in rmports pass | Clifford Wolf | 2017-08-15 | 1 | -30/+33 |
| * | rmports: Now remove ports from cell instances if we optimized them out of tha... | Andrew Zonenberg | 2017-08-14 | 1 | -2/+35 |
| * | ProcessModule is no longer virtual (why was it in the first place?) | Andrew Zonenberg | 2017-08-14 | 1 | -1/+1 |
| * | rmports now works on all modules in the design, not just the top. | Andrew Zonenberg | 2017-08-14 | 1 | -4/+7 |
| * | Updated Makefile to reflect opt_rmports being renamed to rmports | Andrew Zonenberg | 2017-08-14 | 1 | -1/+1 |
| * | Renamed opt_rmports pass to rmports | Andrew Zonenberg | 2017-08-14 | 1 | -5/+5 |
| * | Improved handling of constant connections in opt_rmports | Andrew Zonenberg | 2017-08-14 | 1 | -0/+2 |
| * | Fixed handling of cell ports that aren't wires | Andrew Zonenberg | 2017-08-14 | 1 | -0/+3 |
| * | opt_rmports: Fixed incorrect handling of multi-bit nets | Andrew Zonenberg | 2017-08-14 | 1 | -12/+27 |
| * | Removed commented out debug code | Andrew Zonenberg | 2017-08-14 | 1 | -4/+0 |
| * | Added opt_rmports pass (remove unconnected ports from top-level modules) | Andrew Zonenberg | 2017-08-14 | 2 | -0/+133 |
| * | Add support for set-reset cell variants to opt_rmdff | Clifford Wolf | 2017-08-09 | 1 | -0/+182 |
| * | Add handling of constant reset signals to opt_rmdff | Clifford Wolf | 2017-08-06 | 1 | -1/+23 |
| * | Add consolidation of init attributes to opt_clean, some opt_clean log fixes | Clifford Wolf | 2017-07-29 | 1 | -6/+82 |
| * | Add "opt_expr -fine" feature to remove neutral bits from reduce and logic ope... | Clifford Wolf | 2017-07-26 | 1 | -0/+47 |
| * | Excluded $_TBUF_ from opt_merge pass | Salvador E. Tropea | 2017-07-03 | 1 | -0/+1 |
| * | Fix and_or_buffer optimization in opt_expr for signed operators | Clifford Wolf | 2017-07-01 | 1 | -2/+2 |
