| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | Cope with possibility that D could connect to Q on same cell | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | * | xilinx_srl to use 'slice' features of pmgen for word level | Eddie Hung | 2019-08-23 | 2 | -32/+49 | |
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| | * | Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 4 | -34/+279 | |
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| | * | | Add doc | Eddie Hung | 2019-08-22 | 1 | -1/+14 | |
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| | * | | Add copyright | Eddie Hung | 2019-08-22 | 1 | -0/+1 | |
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| | * | | pmgen to also iterate over all module ports | Eddie Hung | 2019-08-22 | 1 | -2/+4 | |
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| | * | | Remove output_bits | Eddie Hung | 2019-08-22 | 2 | -16/+7 | |
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| | * | | Forgot to set ud_variable.minlen | Eddie Hung | 2019-08-22 | 1 | -0/+1 | |
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| | * | | Do not run xilinx_srl_pm in fixed loop | Eddie Hung | 2019-08-22 | 1 | -28/+24 | |
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| | * | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 1 | -1/+1 | |
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| | * | | | Reuse var | Eddie Hung | 2019-08-21 | 1 | -1/+1 | |
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| | * | | | Revert "Trim shiftx_width when upper bits are 1'bx" | Eddie Hung | 2019-08-21 | 1 | -6/+1 | |
| | | | | | | | | | | | | | | | | | This reverts commit 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb. | |||||
| | * | | | Trim shiftx_width when upper bits are 1'bx | Eddie Hung | 2019-08-21 | 1 | -1/+6 | |
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| | * | | | Add comment | Eddie Hung | 2019-08-21 | 1 | -0/+4 | |
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| | * | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 2 | -14/+164 | |
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| | * | | | Rename pattern to fixed | Eddie Hung | 2019-08-21 | 2 | -10/+10 | |
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| | * | | | attribute -> attr | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
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| | * | | | Use Cell::has_keep_attribute() | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
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| | * | | | xilinx_srl to support FDRE and FDRE_1 | Eddie Hung | 2019-08-21 | 2 | -10/+73 | |
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| | * | | | Fix polarity of EN_POL | Eddie Hung | 2019-08-21 | 1 | -2/+2 | |
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| | * | | | Add CLKPOL == 0 | Eddie Hung | 2019-08-21 | 1 | -0/+2 | |
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| | * | | | Reject if not minlen from inside pattern matcher | Eddie Hung | 2019-08-21 | 2 | -8/+11 | |
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| | * | | | Get wire via SigBit | Eddie Hung | 2019-08-21 | 1 | -4/+4 | |
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| | * | | | Respect \keep on cells or wires | Eddie Hung | 2019-08-21 | 1 | -2/+10 | |
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| | * | | | Add init support | Eddie Hung | 2019-08-21 | 1 | -2/+11 | |
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| | * | | | Fix spacing | Eddie Hung | 2019-08-21 | 1 | -2/+2 | |
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| | * | | | Initial progress on xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -0/+213 | |
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| * | | | | New pmgen requires explicit accept | Eddie Hung | 2019-08-30 | 1 | -0/+2 | |
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| * | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 5 | -34/+281 | |
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| | * \ \ \ | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 10 | -102/+1131 | |
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| | | * | | | | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | | * | | | Fix port hanlding in pmgen | Clifford Wolf | 2019-08-23 | 1 | -4/+3 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | Add pmgen slices and choices | Clifford Wolf | 2019-08-23 | 4 | -28/+276 | |
| | | | |/ | | |/| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | Fix test_pmgen deps | Miodrag Milanovic | 2019-08-21 | 1 | -1/+1 | |
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| | | * | Fix copy-paste typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | Fix compile error | Eddie Hung | 2019-08-20 | 2 | -8/+14 | |
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| * | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 10 | -90/+872 | |
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| | * | | Merge branch 'master' into clifford/pmgen | Clifford Wolf | 2019-08-20 | 1 | -3/+1 | |
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| | | * | | Ignore all generated headers for pmgen pass | Miodrag Milanovic | 2019-08-18 | 1 | -2/+1 | |
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| | * | | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen | Clifford Wolf | 2019-08-19 | 3 | -2/+109 | |
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| | | * | | Revert "Merge pull request #1280 from ↵ | Eddie Hung | 2019-08-12 | 3 | -0/+111 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. | |||||
| | * | | | Refactor pmgen rollback mechanism | Clifford Wolf | 2019-08-17 | 1 | -32/+21 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Improvements in "test_pmgen -generate" | Clifford Wolf | 2019-08-17 | 1 | -3/+23 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Add pmgen "fallthrough" statement | Clifford Wolf | 2019-08-17 | 2 | -3/+17 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Add help() call | Eddie Hung | 2019-08-16 | 1 | -0/+1 | |
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| | * | | | Minor bugfix in "test_pmgen -generate" | Clifford Wolf | 2019-08-16 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Add pmgen finish statement, return number of matches | Clifford Wolf | 2019-08-16 | 4 | -82/+116 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Redesign pmgen backtracking for recursive matching | Clifford Wolf | 2019-08-16 | 2 | -33/+38 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Add pmgen "generate" feature | Clifford Wolf | 2019-08-16 | 3 | -13/+208 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Refactor demo_reduce into test_pmgen | Clifford Wolf | 2019-08-16 | 4 | -14/+83 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
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index : iCE40/yosys | |
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