| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | Add doc for pmgen semioptional statement, Add pmgen changes to CHANGELOG | Clifford Wolf | 2019-08-15 | 1 | -0/+3 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Update pmgen documentation | Clifford Wolf | 2019-08-15 | 1 | -4/+58 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Change pmgen default rule to reject, switch peepopt behavior to accept | Clifford Wolf | 2019-08-15 | 5 | -7/+5 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Add demo_reduce pass to demonstrace recursive pattern matching | Clifford Wolf | 2019-08-15 | 4 | -0/+187 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | Improvements in pmgen for recursive patterns | Clifford Wolf | 2019-08-15 | 4 | -26/+132 | |
| | |/ / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 3 | -111/+0 | |
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| | * | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER | Eddie Hung | 2019-08-07 | 3 | -0/+111 | |
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| * | | | xilinx_dsp to be sensitive to keep attribute | Eddie Hung | 2019-08-15 | 1 | -1/+14 | |
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| * | | | Simplify | Eddie Hung | 2019-08-15 | 1 | -4/+2 | |
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| * | | | ffH -> ffFJKG | Eddie Hung | 2019-08-15 | 2 | -15/+15 | |
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| * | | | Fixes for reverting SigSpec helper functions | Eddie Hung | 2019-08-14 | 2 | -10/+14 | |
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| * | | | Perform C -> PCIN optimisation after pattern matcher | Eddie Hung | 2019-08-13 | 2 | -19/+72 | |
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| * | | | Revert changes to RTLIL::SigSpec methods | Eddie Hung | 2019-08-13 | 2 | -7/+30 | |
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| * | | | Rename to XilinxDspPass | Eddie Hung | 2019-08-13 | 1 | -3/+3 | |
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| * | | Check nusers of DSP output, not whole flop | Eddie Hung | 2019-08-09 | 1 | -1/+1 | |
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| * | | Improve ice40_dsp for non-fully-32-bit adders | Eddie Hung | 2019-08-09 | 1 | -3/+8 | |
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| * | | Another filter -> if | Eddie Hung | 2019-08-09 | 1 | -2/+2 | |
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| * | | Cleanup | Eddie Hung | 2019-08-09 | 2 | -18/+18 | |
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| * | | Pack partial-product adder DSP48E1 packing | Eddie Hung | 2019-08-09 | 2 | -10/+79 | |
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| * | | Fix check | Eddie Hung | 2019-08-09 | 1 | -4/+6 | |
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| * | | Revert "Fix typo" | Eddie Hung | 2019-08-09 | 1 | -1/+1 | |
| | | | | | | | | | This reverts commit e3c39cc450a0317ad7e8234bb866d55465548c9c. | |||||
| * | | Remove muxY and ffY for now | Eddie Hung | 2019-08-08 | 2 | -35/+33 | |
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| * | | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing | Eddie Hung | 2019-08-08 | 3 | -39/+83 | |
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| * | | Only pack registers if {A,B,P}REG = 0, do not pack $dffe | Eddie Hung | 2019-08-08 | 1 | -3/+6 | |
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| * | | Disable $dffe | Eddie Hung | 2019-08-08 | 1 | -8/+8 | |
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| * | | Fix compile error | Eddie Hung | 2019-08-07 | 1 | -2/+2 | |
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| * | | Do not SigSpec::extract() beyond bounds | Eddie Hung | 2019-08-07 | 2 | -8/+10 | |
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| * | | Do not pack registers if (* keep *) | Eddie Hung | 2019-08-07 | 1 | -0/+20 | |
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| * | | Add comment about supporting $dffe in ice40_dsp | Eddie Hung | 2019-08-01 | 1 | -0/+1 | |
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| * | | Pack P register properly | Eddie Hung | 2019-08-01 | 1 | -2/+4 | |
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| * | | Cope with sign extension in mul2dsp | Eddie Hung | 2019-08-01 | 2 | -14/+14 | |
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| * | | CO is sign extension only if signed multiplier | Eddie Hung | 2019-08-01 | 1 | -1/+6 | |
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| * | | Fix typo | Eddie Hung | 2019-08-01 | 1 | -1/+1 | |
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| * | | Restore old CO behaviour | Eddie Hung | 2019-07-31 | 1 | -6/+7 | |
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| * | | Pop the CO bit from O | Eddie Hung | 2019-07-26 | 1 | -1/+3 | |
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| * | | Allow adders/accumulators with 33 bits using CO output | Eddie Hung | 2019-07-26 | 1 | -3/+8 | |
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| * | | Eliminate warnings by sizing O correctly | Eddie Hung | 2019-07-23 | 1 | -1/+5 | |
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| * | | Fix muxAB logic | Eddie Hung | 2019-07-23 | 1 | -3/+2 | |
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| * | | Remove debug print | Eddie Hung | 2019-07-23 | 1 | -1/+1 | |
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| * | | Simplify and fix for MACs | Eddie Hung | 2019-07-23 | 2 | -56/+38 | |
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| * | | Fix typo | Eddie Hung | 2019-07-23 | 1 | -13/+21 | |
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| * | | Fix spacing | Eddie Hung | 2019-07-22 | 1 | -2/+2 | |
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| * | | Pack hi and lo registers separately | Eddie Hung | 2019-07-22 | 2 | -39/+70 | |
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| * | | Rename according to vendor doc TN1295 | Eddie Hung | 2019-07-22 | 2 | -55/+55 | |
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| * | | Pack Y register | Eddie Hung | 2019-07-22 | 2 | -22/+38 | |
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| * | | Pack adders not just accumulators | Eddie Hung | 2019-07-22 | 2 | -16/+33 | |
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| * | | Restore old ffY behaviour | Eddie Hung | 2019-07-19 | 1 | -16/+5 | |
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| * | | Cleanup | Eddie Hung | 2019-07-19 | 1 | -5/+5 | |
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| * | | Fine tune ice40_dsp.pmg, add support for packing subsets of registers | Eddie Hung | 2019-07-19 | 4 | -35/+47 | |
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| * | | Add support for ice40 signed multipliers | Eddie Hung | 2019-07-19 | 1 | -13/+8 | |
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index : iCE40/yosys | |
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