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* Move GENERATE_PATTERN macro to separate utility headerClifford Wolf2019-10-163-128/+157
* Disable left-over log_debug in peepopt_dffmux.pmgClifford Wolf2019-10-161-1/+1
* Merge pull request #1432 from YosysHQ/eddie/fix1427Eddie Hung2019-10-081-47/+81
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| * Fix broken CI, check reset even for constants, trim rstmuxEddie Hung2019-10-021-23/+26
| * Refactor peepopt_dffmux and be sensitive to \init when trimmingEddie Hung2019-10-021-32/+63
* | Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_commentsEddie Hung2019-10-084-68/+356
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| * | Missed thisEddie Hung2019-10-051-3/+4
| * | Add comment on why we have to match for clock-enable/reset muxesEddie Hung2019-10-053-3/+11
| * | Add note on pattern detectorEddie Hung2019-10-051-3/+7
| * | Add comments for xilinx_dsp_cascadeEddie Hung2019-10-041-12/+100
| * | Improve comments for xilinx_dsp_CREGEddie Hung2019-10-041-6/+7
| * | Fix commentEddie Hung2019-10-041-1/+1
| * | Restore optimisation for sigM.empty()Eddie Hung2019-10-041-1/+4
| * | Retry on fixing TODOsEddie Hung2019-10-042-13/+1
| * | Revert "Fix TODOs"Eddie Hung2019-10-042-0/+20
| * | More comments, cleanupEddie Hung2019-10-042-41/+108
| * | Fix TODOsEddie Hung2019-10-042-20/+0
| * | ConsistencyEddie Hung2019-10-041-3/+3
| * | Add comments for xilinx_dspEddie Hung2019-10-043-6/+134
* | | Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarryClifford Wolf2019-10-061-0/+4
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| * | | Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolfEddie Hung2019-10-051-0/+4
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* | | Update README.mdClifford Wolf2019-10-051-1/+1
* | | Merge pull request #1436 from YosysHQ/mmicko/msvc_fixMiodrag Milanović2019-10-051-0/+1
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| * | Fixes for MSVC buildMiodrag Milanovic2019-10-041-0/+1
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* / Fix xilinx_dsp for unsigned extensionsEddie Hung2019-10-041-1/+3
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* Ooops AREG and BREG to default to -1Eddie Hung2019-09-271-2/+2
* Update doc with max cascade chain of 20Eddie Hung2019-09-261-2/+4
* Do not always zero out C (e.g. during cascade breaks)Eddie Hung2019-09-262-7/+3
* Update docEddie Hung2019-09-261-1/+2
* Zero out portsEddie Hung2019-09-261-2/+2
* xilinx_dsp_cascade to also cascade AREG and BREGEddie Hung2019-09-262-454/+172
* Try recursive pmgen for P cascadeEddie Hung2019-09-261-88/+118
* CREG to check for \keepEddie Hung2019-09-261-0/+3
* Remove newlineEddie Hung2019-09-261-1/+0
* Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)Eddie Hung2019-09-251-1/+5
* Reject if (* init *) presentEddie Hung2019-09-252-0/+6
* Rework xilinx_dsp postAdd for new wreduce callEddie Hung2019-09-251-3/+3
* Fix memory issue since SigSpec& could be invalidatedEddie Hung2019-09-251-6/+10
* unextend only used in initEddie Hung2019-09-251-2/+1
* Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-251-5/+4
* Set [AB]CASCREG to legal valuesEddie Hung2019-09-231-6/+10
* Comment to explain separating CREG packingEddie Hung2019-09-231-0/+8
* Separate out CREG packing into new pattern, to avoid conflict with PREGEddie Hung2019-09-234-46/+273
* Move log_debug("\n") laterEddie Hung2019-09-231-1/+1
* Move unextend initialisation laterEddie Hung2019-09-231-12/+9
* Use new port() overload once moreEddie Hung2019-09-231-2/+2
* Use new port/param overload in pmgEddie Hung2019-09-204-22/+22
* Output pattern matcher items as log_debug()Eddie Hung2019-09-202-31/+27
* OPMODE is port not paramEddie Hung2019-09-201-7/+6
* Do not run xilinx_dsp_cascadeAB for nowEddie Hung2019-09-201-1/+2
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