Commit message (Collapse) | Author | Age | Files | Lines | ||
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* | | Cleanup | Miodrag Milanovic | 2022-03-02 | 1 | -10/+7 | |
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* | | Refactor sim output writers | Miodrag Milanovic | 2022-02-28 | 1 | -213/+257 | |
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* | | Quick fix | Miodrag Milanovic | 2022-02-28 | 1 | -0/+2 | |
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* | | Add writing of aiw files to "sim" command | Claire Xenia Wolf | 2022-02-28 | 1 | -1/+87 | |
| | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
* | | Hotfix in AIGER witness reader state machine | Claire Xenia Wolf | 2022-02-28 | 1 | -0/+1 | |
|/ | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
* | Support extended aiw format | Miodrag Milanovic | 2022-02-27 | 1 | -23/+44 | |
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* | Fix for last clock edge data | Miodrag Milanovic | 2022-02-25 | 1 | -3/+1 | |
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* | Experimental sim changes | Claire Xenia Wolf | 2022-02-25 | 1 | -20/+22 | |
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* | Merge pull request #3211 from YosysHQ/micko/witness | Claire Xen | 2022-02-22 | 1 | -1/+96 | |
|\ | | | | | Add support for AIGER witness files in "sim" command | |||||
| * | Fix cycle 0 in aiger witness co-simulation | Claire Xenia Wolf | 2022-02-18 | 1 | -12/+15 | |
| | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| * | Added AIGER witness file co simulation | Miodrag Milanovic | 2022-02-18 | 1 | -1/+93 | |
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* | | Fix handling of ce_over_srst | Miodrag Milanovic | 2022-02-21 | 1 | -3/+2 | |
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* | simplify logic of handling flip-flops and latches | Miodrag Milanovic | 2022-02-18 | 1 | -118/+42 | |
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* | Review cleanup | Miodrag Milanovic | 2022-02-17 | 1 | -6/+5 | |
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* | Add support for various ff/latch cells simulation | Miodrag Milanovic | 2022-02-16 | 1 | -60/+204 | |
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* | Merge branch 'master' into clk2ff-better-names | Claire Xen | 2022-02-11 | 14 | -88/+534 | |
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| * | Merge pull request #3185 from YosysHQ/micko/co_sim | Miodrag Milanović | 2022-02-07 | 1 | -21/+430 | |
| |\ | | | | | | | Add co-simulation in sim pass | |||||
| | * | Error detection for co-simulation | Miodrag Milanovic | 2022-02-04 | 1 | -0/+3 | |
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| | * | bug fix and cleanups | Miodrag Milanovic | 2022-02-04 | 1 | -5/+5 | |
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| | * | respect hide_internal flag | Miodrag Milanovic | 2022-02-02 | 1 | -1/+1 | |
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| | * | unify cycles counting and cleanup | Miodrag Milanovic | 2022-02-02 | 1 | -36/+35 | |
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| | * | added stimulus mode and param check | Miodrag Milanovic | 2022-02-02 | 1 | -5/+31 | |
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| | * | error when no signal found | Miodrag Milanovic | 2022-01-31 | 1 | -0/+2 | |
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| | * | Cleanup | Miodrag Milanovic | 2022-01-31 | 1 | -1/+1 | |
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| | * | Compare bits when not all are defined | Miodrag Milanovic | 2022-01-31 | 1 | -3/+17 | |
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| | * | Cleanup | Miodrag Milanovic | 2022-01-31 | 1 | -2/+2 | |
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| | * | message update | Miodrag Milanovic | 2022-01-31 | 1 | -1/+1 | |
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| | * | Display simulation time data | Miodrag Milanovic | 2022-01-31 | 1 | -1/+4 | |
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| | * | Use edges when explicit | Miodrag Milanovic | 2022-01-31 | 1 | -1/+5 | |
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| | * | Updating initial state and checks | Miodrag Milanovic | 2022-01-31 | 1 | -15/+28 | |
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| | * | Fix scope | Miodrag Milanovic | 2022-01-31 | 1 | -1/+1 | |
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| | * | check if stop before start | Miodrag Milanovic | 2022-01-28 | 1 | -0/+3 | |
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| | * | set initial state, only flip-flops | Miodrag Milanovic | 2022-01-28 | 1 | -1/+28 | |
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| | * | ignore not found private signals | Miodrag Milanovic | 2022-01-28 | 1 | -0/+3 | |
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| | * | recursive check | Miodrag Milanovic | 2022-01-28 | 1 | -26/+34 | |
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| | * | Do actual compare | Miodrag Milanovic | 2022-01-28 | 1 | -5/+16 | |
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| | * | Add more options and time handling | Miodrag Milanovic | 2022-01-28 | 1 | -2/+103 | |
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| | * | Display values of outputs | Miodrag Milanovic | 2022-01-26 | 1 | -12/+10 | |
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| | * | Check if stimulated | Miodrag Milanovic | 2022-01-26 | 1 | -0/+14 | |
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| | * | Read fst and use data to set inputs | Miodrag Milanovic | 2022-01-26 | 1 | -10/+92 | |
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| | * | Add ability to write to FST file | Miodrag Milanovic | 2022-01-26 | 1 | -11/+109 | |
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| * | | Add $bmux and $demux cells. | Marcelina Kościelnicka | 2022-01-28 | 1 | -0/+6 | |
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| * | FfData: some refactoring. | Marcelina Kościelnicka | 2021-10-07 | 2 | -26/+22 | |
| | | | | | | | | | | | | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases | |||||
| * | kernel/ff: Refactor FfData to enable FFs with async load. | Marcelina Kościelnicka | 2021-10-02 | 2 | -31/+64 | |
| | | | | | | | | | | | | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load | |||||
| * | memory: Introduce $meminit_v2 cell, with EN input. | Marcelina Kościelnicka | 2021-07-28 | 1 | -0/+1 | |
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| * | Use HTTPS for website links, gatecat email | Claire Xenia Wolf | 2021-06-09 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g; | |||||
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 14 | -15/+15 | |
| | | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | |||||
| * | sim: Add wide port support. | Marcelina Kościelnicka | 2021-05-25 | 1 | -3/+3 | |
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| * | kernel/rtlil: Extract some helpers for checking memory cell types. | Marcelina Kościelnicka | 2021-05-22 | 1 | -1/+1 | |
| | | | | | | | | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list. | |||||
| * | sim: Avoid a crash on empty cell connection. | Marcelina Kościelnicka | 2021-03-08 | 1 | -1/+1 | |
| | | | | | | | | Fixes #2513. |