| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | Explicitly order function arguments | Eddie Hung | 2019-09-13 | 1 | -4/+15 | |
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| | * | Add -match-init option to dff2dffs. | Marcin Kościelnicki | 2019-09-11 | 1 | -3/+26 | |
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| | * | techmap: Add support for extracting init values of ports | Marcin Kościelnicki | 2019-09-07 | 1 | -1/+70 | |
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| | * | Merge pull request #1312 from YosysHQ/xaig_arrival | Eddie Hung | 2019-09-05 | 1 | -42/+16 | |
| | |\ | | | | | | | Allow arrival times of sequential outputs to be specified to abc9 | |||||
| | | * | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-30 | 1 | -16/+10 | |
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| | | * \ | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-30 | 1 | -1/+1 | |
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| | | * | | | Use a dummy box file if none specified | Eddie Hung | 2019-08-28 | 1 | -3/+8 | |
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| | | * | | | Merge branch 'eddie/xilinx_srl' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -174/+5 | |
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| | | * \ \ \ | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-28 | 4 | -88/+456 | |
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| | | * | | | | | Cleanup | Eddie Hung | 2019-08-23 | 1 | -130/+59 | |
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| | | * | | | | | Merge branch 'eddie/fix_techmap' into xaig_arrival | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| | | * | | | | | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 | |
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| | * | | | | | | | Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes ↵ | Clifford Wolf | 2019-09-05 | 1 | -8/+24 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | #1220 Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | Add flatten handling of pre-existing wires as created by interfaces, fixes #1145 | Clifford Wolf | 2019-09-05 | 1 | -8/+20 | |
| | | |_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | Merge pull request #1340 from YosysHQ/eddie/abc_no_clean | Eddie Hung | 2019-08-30 | 1 | -16/+10 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | abc9 to not call "clean" at end of run (often called outside) | |||||
| | | * | | | | | | Output has priority over input when stitching in abc9 | Eddie Hung | 2019-08-29 | 1 | -13/+10 | |
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| | | * | | | | | | abc9 to not call "clean" at end of run (often called outside) | Eddie Hung | 2019-08-29 | 1 | -3/+0 | |
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| | * | | | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-30 | 1 | -1/+1 | |
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| | | * | | | | Fix typo that's gone unnoticed for 5 months!?! | Eddie Hung | 2019-08-29 | 1 | -1/+1 | |
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| | * | | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-28 | 4 | -88/+456 | |
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| | | * | | | Fix typo | Clifford Wolf | 2019-08-28 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | Add "paramap" pass | Clifford Wolf | 2019-08-28 | 1 | -67/+118 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | improve clkbuf_inhibit propagation upwards through hierarchy | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+12 | |
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| | | * | | | clkbufmap to only check clkbuf_inhibit if no selection given | Eddie Hung | 2019-08-23 | 1 | -5/+18 | |
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| | | * | | | Review comment from @cliffordwolf | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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| | | * | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 20 | -311/+350 | |
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| | | * | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-16 | 26 | -1135/+1130 | |
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| | | * | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 2 | -28/+9 | |
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| | | * | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 2 | -29/+4 | |
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| | | * | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 3 | -20/+356 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | |||||
| | * | | | | | Actually, there might not be any harm in updating sigmap... | Eddie Hung | 2019-08-22 | 1 | -3/+1 | |
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| | * | | | | | Add comment as per @cliffordwolf | Eddie Hung | 2019-08-22 | 1 | -0/+11 | |
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| | * | | | | | Revert "Try way that doesn't involve creating a new wire" | Eddie Hung | 2019-08-22 | 1 | -15/+10 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b. | |||||
| | * | | | | | Try way that doesn't involve creating a new wire | Eddie Hung | 2019-08-22 | 1 | -10/+15 | |
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| | * | | | | | If d_bit already in sigbit_chain_next, create extra wire | Eddie Hung | 2019-08-22 | 1 | -3/+6 | |
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| | * | | | | | Remove `shregmap -tech xilinx` additions | Eddie Hung | 2019-08-22 | 1 | -189/+8 | |
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| | * | | | | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| | * | | | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 | |
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| * | | | | | Revert "Remove sequential extension" | Eddie Hung | 2019-08-20 | 1 | -20/+68 | |
| | |_|_|/ |/| | | | | | | | | | | | This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c. | |||||
| * | | | | Remove sequential extension | Eddie Hung | 2019-08-20 | 1 | -68/+20 | |
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| * | | | | retime_mode -> dff_mode | Eddie Hung | 2019-08-20 | 1 | -7/+7 | |
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| * | | | | Fix use of {CLK,EN}_POLARITY, also add a FIXME | Eddie Hung | 2019-08-20 | 1 | -65/+13 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 1 | -6/+6 | |
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| | * | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 1 | -43/+80 | |
| | |\ \ \ | | | | | | | | | | | Refactor abc9 to use port attributes, not module attributes | |||||
| | | * | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -6/+6 | |
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| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-19 | 1 | -1/+1 | |
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| | * | | | | Fix typo | Eddie Hung | 2019-08-19 | 1 | -1/+1 | |
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| * | | | | | Remove debug | Eddie Hung | 2019-08-19 | 1 | -1/+1 | |
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| * | | | | | Add (* abc_arrival *) attribute | Eddie Hung | 2019-08-19 | 1 | -1/+1 | |
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| * | | | | | Move from cell attr to module attr | Eddie Hung | 2019-08-19 | 1 | -24/+64 | |
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index : iCE40/yosys | |
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