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* | | Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-patternclairexen2020-08-201-4/+32
|\ \ \ | |_|/ |/| | techmap: Add support for [] wildcards in techmap_celltype.
| * | techmap: Add support for [] wildcards in techmap_celltype.Marcelina Kościelnicka2020-08-021-4/+32
| |/ | | | | | | Fixes #1826.
* / Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-1/+1
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* Add dffunmap pass.Marcelina Kościelnicka2020-07-312-0/+108
| | | | | To be used with backends that cannot deal with fancy FF types (like blif or smt).
* techmap: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-41/+4
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* shregmap: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-39/+10
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* abc: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-25/+6
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* dffinit: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-41/+7
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* zinit: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-43/+11
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* dfflegalize: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-80/+25
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* techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-0/+6
| | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* dfflegalize: Gather init values from all wires.Marcelina Kościelnicka2020-07-121-1/+1
| | | | Skipping non-selected wires is unsound in an obvious way.
* dfflibmap: Refactor to use dfflegalize internally.Marcelina Kościelnicka2020-07-091-211/+78
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* clkbufmap: improve input pad handling.Marcelina Kościelnicka2020-07-091-17/+39
| | | | | | - allow inserting only the input pad cell - do not insert the usual buffer if the input pad already acts as a buffer
* dfflegalize: Add special support for const-D latches.Marcelina Kościelnicka2020-07-091-0/+18
| | | | | | Those can be created by `opt_dff` when optimizing `$adff` with const clock, or with D == Q. Make dfflegalize do the opposite transform when such dlatches would be otherwise unimplementable.
* dfflegalize: typo fixMarcelina Kościelnicka2020-07-071-1/+1
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* Naming fixes.Marcelina Kościelnicka2020-07-052-2/+2
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* dfflegalize: Prefer mapping dff to sdff before adffMarcelina Kościelnicka2020-07-051-1/+1
| | | | | | This ensures that, when both sync and async FFs are available and abc9 is involved, the sync FFs will be used, and will thus remain available for sequential synthesis.
* abc9: only techmap (* abc9_flop *) modulesEddie Hung2020-07-041-1/+1
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* abc9: techmap from user design to allow abc9_flop modules to be composedEddie Hung2020-07-041-1/+1
| | | | from other primitives
* Add newlines to help text for dfflegalizeRupert Swarbrick2020-07-031-11/+11
| | | | | | | | | | | | | I think these were probably missed by accident. Spotted because GCC spits out lots of messages like this: passes/techmap/dfflegalize.cc:114:7: warning: zero-length gnu_printf format string [-Wformat-zero-length] 114 | log(""); | ^~ (because we tell GCC that the first argument to log() looks like a printf control string in log.h, and a zero length such string triggers a warning).
* Add dfflegalize pass.Marcelina Kościelnicka2020-07-012-0/+1357
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* techmap: don't drop attributes on replaced cells.whitequark2020-06-291-2/+3
| | | | | | This was introduced in 76c4ee4ea5cb6a3dc214f66237af22a1bedda010. Fixes #2204.
* Merge pull request #2168 from whitequark/assert-unused-exprsclairexen2020-06-252-7/+7
|\ | | | | Use (and ignore) the expression provided to log_assert in NDEBUG builds
| * Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().whitequark2020-06-192-7/+7
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* | simplemap: Fix $dffsre mapping.Marcelina Kościelnicka2020-06-231-1/+1
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* | Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-233-43/+73
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* | Add new FF types to simplemap.Marcelina Kościelnicka2020-06-231-8/+133
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* Use C++11 final/override keywords.whitequark2020-06-1834-77/+77
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* msvc does not support designated initializers in structsAnonymous Maarten2020-06-171-5/+5
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* flatten: accept processes.whitequark2020-06-091-8/+8
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* flatten: preserve original object names via hdlname attribute.whitequark2020-06-081-5/+16
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* flatten: only prepend $flatten once per wire.whitequark2020-06-081-2/+6
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* flatten: make hygienic.whitequark2020-06-081-155/+116
| | | | | | | | | | | | | | | | | | | | Before this commit, `flatten` matched the template objects with the newly created objects solely by their name. Because of this, it could be confused by code such as: module bar(); $dff a(); endmodule module foo(); bar b(); $dff \b.a (); endmodule After this commit, `flatten` avoids every possible case of name collision. Fixes #2106.
* Merge pull request #2105 from whitequark/split-flatten-off-techmapclairexen2020-06-083-325/+527
|\ | | | | Split `flatten` from `techmap` and simplify it
| * flatten: clean up log messages.whitequark2020-06-041-1/+1
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| * flatten: topologically sort modules.whitequark2020-06-041-55/+47
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| * flatten: simplify.whitequark2020-06-041-43/+7
| | | | | | | | | | | | | | `flatten` cannot derive modules in most cases because that would just yield processes, and it does not support `-autoproc`; in practice `flatten` has to be preceded by a call to `hierarchy`, which makes deriving unnecessary.
| * flatten: simplify. NFC.whitequark2020-06-041-7/+3
| | | | | | | | Remove redundant sigmaps.
| * flatten: simplify.whitequark2020-06-041-35/+0
| | | | | | | | | | Flattening does not benefit from topologically sorting cells within a module when processing them.
| * flatten: simplify. NFC.whitequark2020-06-041-11/+4
| | | | | | | | | | Flatten is non-recursive and doesn't need to keep track of handled cells.
| * flatten: simplify. NFC.whitequark2020-06-041-6/+4
| | | | | | | | Flattening always does "non-recursive" mapping.
| * flatten: simplify. NFC.whitequark2020-06-041-73/+39
| | | | | | | | The `celltypeMap` always maps `x` to `{x}`.
| * flatten: simplify. NFC.whitequark2020-06-041-8/+8
| | | | | | | | The `design` and `map` designs are always the same when flattening.
| * RTLIL: factor out RTLIL::Module::addMemory. NFC.whitequark2020-06-042-14/+2
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| * flatten: rename techmap-related stuff. NFC.whitequark2020-06-041-16/+16
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| * techmap, flatten: remove dead options.whitequark2020-06-042-928/+212
| | | | | | | | | | | | After splitting the passes, some options can never be activated, and most conditions involving them become dead. Remove them, and also all of the newly dead code.
| * flatten: split from techmap.whitequark2020-06-033-93/+1149
| | | | | | | | | | | | | | Although the two passes started out very similar, they diverged over time and now have little in common. Moreover, `techmap` is extremely complex while `flatten` does not have to be, and this complexity interferes with improving `flatten`.
* | Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-19/+60
|\ \ | | | | | | abc9: -dff improvements
| * | abc9_ops: fix commentEddie Hung2020-05-301-1/+1
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