| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | | | | | | | | | | improve clkbuf_inhibit propagation upwards through hierarchy | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+12 | |
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| | * | | | | | | | | | | | | | clkbufmap to only check clkbuf_inhibit if no selection given | Eddie Hung | 2019-08-23 | 1 | -5/+18 | |
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| | * | | | | | | | | | | | | | Review comment from @cliffordwolf | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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| | * | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 20 | -311/+350 | |
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| | * | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-16 | 26 | -1135/+1130 | |
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| | * | | | | | | | | | | | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 2 | -28/+9 | |
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| | * | | | | | | | | | | | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 2 | -29/+4 | |
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| | * | | | | | | | | | | | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 3 | -20/+356 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | |||||
| * | | | | | | | | | | | | | | | Actually, there might not be any harm in updating sigmap... | Eddie Hung | 2019-08-22 | 1 | -3/+1 | |
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| * | | | | | | | | | | | | | | | Add comment as per @cliffordwolf | Eddie Hung | 2019-08-22 | 1 | -0/+11 | |
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| * | | | | | | | | | | | | | | | Revert "Try way that doesn't involve creating a new wire" | Eddie Hung | 2019-08-22 | 1 | -15/+10 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b. | |||||
| * | | | | | | | | | | | | | | | Try way that doesn't involve creating a new wire | Eddie Hung | 2019-08-22 | 1 | -10/+15 | |
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| * | | | | | | | | | | | | | | | If d_bit already in sigbit_chain_next, create extra wire | Eddie Hung | 2019-08-22 | 1 | -3/+6 | |
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| * | | | | | | | | | | | | | | | Remove `shregmap -tech xilinx` additions | Eddie Hung | 2019-08-22 | 1 | -189/+8 | |
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| * | | | | | | | | | | | | | | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| * | | | | | | | | | | | | | | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 | |
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| * | | | | | | | | | | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 1 | -43/+80 | |
| |\ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|_|_|_|_|/ |/| | | | | | | | | | | | | Refactor abc9 to use port attributes, not module attributes | |||||
| | * | | | | | | | | | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -6/+6 | |
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| | * | | | | | | | | | | | Use ID() | Eddie Hung | 2019-08-16 | 1 | -3/+3 | |
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| | * | | | | | | | | | | | Compute abc_scc_break and move CI/CO outside of each abc9 | Eddie Hung | 2019-08-16 | 1 | -43/+80 | |
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| * | | | | | | | | | | | Fix typo | Eddie Hung | 2019-08-19 | 1 | -1/+1 | |
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| * | | | | | | | | | | Merge pull request #1283 from YosysHQ/clifford/fix1255 | Clifford Wolf | 2019-08-17 | 1 | -1/+1 | |
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | Fix various NDEBUG compiler warnings | |||||
| | * \ \ \ \ \ \ \ \ \ | Merge branch 'master' into clifford/fix1255 | Clifford Wolf | 2019-08-15 | 1 | -2/+2 | |
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| | * | | | | | | | | | | | Fix various NDEBUG compiler warnings, closes #1255 | Clifford Wolf | 2019-08-13 | 1 | -1/+1 | |
| | | |_|/ / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | | | Merge pull request #1300 from YosysHQ/eddie/cleanup2 | Clifford Wolf | 2019-08-17 | 20 | -262/+262 | |
| |\ \ \ \ \ \ \ \ \ \ \ | |_|_|/ / / / / / / / |/| | | | | | | | | | | Use ID::{A,B,Y,keep,blackbox,whitebox} instead of ID() | |||||
| | * | | | | | | | | | | Use ID::keep more liberally too | Eddie Hung | 2019-08-15 | 4 | -9/+9 | |
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| | * | | | | | | | | | | Use more ID::{A,B,Y,blackbox,whitebox} | Eddie Hung | 2019-08-15 | 20 | -253/+253 | |
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| * | | | | | | | | | | | Merge pull request #1302 from mmicko/dfflibmap_regression | Clifford Wolf | 2019-08-16 | 2 | -10/+10 | |
| |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | DFFLIBMAP pass regression fix | |||||
| | * | | | | | | | | | | | Regression in abc9 | Miodrag Milanovic | 2019-08-16 | 1 | -1/+1 | |
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| | * | | | | | | | | | | | Just needed IDs to be IdString | Miodrag Milanovic | 2019-08-16 | 1 | -9/+9 | |
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| * / / / / / / / / / / | Add missing NMUX to "abc -g" handling | Clifford Wolf | 2019-08-16 | 1 | -0/+1 | |
| |/ / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | | ID(\\.*) -> ID(.*) | Eddie Hung | 2019-08-15 | 25 | -766/+766 | |
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| * | | | | | | | | | | Transform all "\\*" identifiers into ID() | Eddie Hung | 2019-08-15 | 25 | -782/+782 | |
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| * | | | | | | | | | | Transform "$.*" to ID("$.*") in passes/techmap | Eddie Hung | 2019-08-15 | 24 | -367/+362 | |
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| * | | | | | | | | | | More use of IdString::in() | Eddie Hung | 2019-08-15 | 3 | -10/+9 | |
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| * | | | | | | | | | AND with an inverted input, causes X{,N}OR output to be inverted too | Eddie Hung | 2019-08-14 | 1 | -2/+2 | |
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| * | | | | | | | | | Revert "Only sort leaves on non-ANDNOT/ORNOT cells" | Eddie Hung | 2019-08-14 | 1 | -7/+6 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 5ec5f6dec7d4cdcfd9e1a2cda999886605778400. | |||||
| * | | | | | | | | | Only sort leaves on non-ANDNOT/ORNOT cells | Eddie Hung | 2019-08-14 | 1 | -6/+7 | |
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| * | | | | | | | | | Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves" | Eddie Hung | 2019-08-14 | 1 | -4/+8 | |
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| * | | | | | | | | | Since $_ANDNOT_ is not symmetric, do not sort leaves | Eddie Hung | 2019-08-12 | 1 | -8/+4 | |
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| * | | | | | | | | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 11 | -67/+67 | |
| |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | Cleanup a few barnacles across codebase | |||||
| | * | | | | | | | | substr() -> compare() | Eddie Hung | 2019-08-07 | 5 | -28/+28 | |
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| | * | | | | | | | | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 4 | -16/+16 | |
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| | * | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/cleanup | Eddie Hung | 2019-08-07 | 1 | -22/+20 | |
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| | * | | | | | | | | | stoi -> atoi | Eddie Hung | 2019-08-07 | 11 | -39/+39 | |
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| | * | | | | | | | | | Use std::stoi instead of atoi(<str>.c_str()) | Eddie Hung | 2019-08-06 | 9 | -32/+32 | |
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| | * | | | | | | | | | Use State::S{0,1} | Eddie Hung | 2019-08-06 | 1 | -1/+1 | |
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| | * | | | | | | | | | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 6 | -17/+17 | |
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| * | | | | | | | | | | Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g ↵ | Clifford Wolf | 2019-08-09 | 1 | -15/+54 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | all", fixes #1273 Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | | | | | Add comment | Eddie Hung | 2019-08-07 | 1 | -2/+3 | |
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