| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | | | Use "abc9_period" attribute for delay target | Eddie Hung | 2019-10-07 | 1 | -3/+24 | |
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| * | | | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 1 | -30/+6 | |
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| * | | | | | Fix from merge | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
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| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-04 | 2 | -3/+15 | |
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| | * | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -3/+13 | |
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| | * | | | | Fix xilinx_dsp for unsigned extensions | Eddie Hung | 2019-10-04 | 1 | -1/+3 | |
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| * | | | | Fix merge issues | Eddie Hung | 2019-10-04 | 2 | -10/+2 | |
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| * | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 1 | -68/+67 | |
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| | * | | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 1 | -65/+65 | |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-03 | 2 | -27/+69 | |
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| | * | | Merge pull request #1422 from YosysHQ/eddie/aigmap_select | Clifford Wolf | 2019-10-03 | 1 | -6/+40 | |
| | |\ \ | | | | | | | | | Add -select option to aigmap | |||||
| | | * | | Add -select option to aigmap | Eddie Hung | 2019-09-30 | 1 | -6/+40 | |
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| | * | | Merge pull request #1429 from YosysHQ/clifford/checkmapped | Clifford Wolf | 2019-10-03 | 1 | -27/+55 | |
| | |\ \ | | | | | | | | | Add "check -mapped" | |||||
| | | * | | Add "check -allow-tbuf" | Clifford Wolf | 2019-10-03 | 1 | -8/+22 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | Add "check -mapped" | Clifford Wolf | 2019-10-02 | 1 | -21/+35 | |
| | | |/ | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf | Eddie Hung | 2019-10-02 | 1 | -4/+8 | |
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| | * | | techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias | Eddie Hung | 2019-09-30 | 1 | -0/+10 | |
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| * | | No need to punch ports at all | Eddie Hung | 2019-09-30 | 1 | -13/+0 | |
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| * | | Resolve FIXME on calling proc just once | Eddie Hung | 2019-09-30 | 1 | -2/+2 | |
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| * | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 1 | -0/+8 | |
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| * | | Add comment | Eddie Hung | 2019-09-30 | 1 | -0/+1 | |
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| * | | scc call on active module module only, plus cleanup | Eddie Hung | 2019-09-30 | 1 | -21/+16 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 3 | -2/+6 | |
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| | * | Update doc for equiv_opt | Eddie Hung | 2019-09-30 | 1 | -2/+3 | |
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| | * | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in | Miodrag Milanović | 2019-09-30 | 1 | -1/+1 | |
| | |\ | | | | | | | Open aig frontend as binary file | |||||
| | | * | Open aig frontend as binary file | Miodrag Milanovic | 2019-09-29 | 1 | -1/+1 | |
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| | * | | Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+2 | |
| | |\ \ | | | | | | | | | equiv_opt to call async2sync when not -multiclock like SymbiYosys | |||||
| | | * | | equiv_opt to call async2sync when not -multiclock like SymbiYosys | Eddie Hung | 2019-09-27 | 1 | -0/+2 | |
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| | * | | Fix $dlatch handling in async2sync | Clifford Wolf | 2019-09-30 | 1 | -0/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 12 | -229/+2498 | |
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| | * | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 12 | -229/+2498 | |
| | |\ \ | | |/ | |/| | DSP inference for Xilinx (improved for ice40, initial support for ecp5) | |||||
| | | * | Ooops AREG and BREG to default to -1 | Eddie Hung | 2019-09-27 | 1 | -2/+2 | |
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| | | * | Update doc with max cascade chain of 20 | Eddie Hung | 2019-09-26 | 1 | -2/+4 | |
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| | | * | Do not always zero out C (e.g. during cascade breaks) | Eddie Hung | 2019-09-26 | 2 | -7/+3 | |
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| | | * | Update doc | Eddie Hung | 2019-09-26 | 1 | -1/+2 | |
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| | | * | Zero out ports | Eddie Hung | 2019-09-26 | 1 | -2/+2 | |
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| | | * | xilinx_dsp_cascade to also cascade AREG and BREG | Eddie Hung | 2019-09-26 | 2 | -454/+172 | |
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| | | * | Try recursive pmgen for P cascade | Eddie Hung | 2019-09-26 | 1 | -88/+118 | |
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| | | * | CREG to check for \keep | Eddie Hung | 2019-09-26 | 1 | -0/+3 | |
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| | | * | Remove newline | Eddie Hung | 2019-09-26 | 1 | -1/+0 | |
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| | | * | Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed) | Eddie Hung | 2019-09-25 | 1 | -1/+5 | |
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| | | * | Reject if (* init *) present | Eddie Hung | 2019-09-25 | 2 | -0/+6 | |
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| | | * | Rework xilinx_dsp postAdd for new wreduce call | Eddie Hung | 2019-09-25 | 1 | -3/+3 | |
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| | | * | Fix memory issue since SigSpec& could be invalidated | Eddie Hung | 2019-09-25 | 1 | -6/+10 | |
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| | | * | unextend only used in init | Eddie Hung | 2019-09-25 | 1 | -2/+1 | |
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| | | * | Call 'wreduce' after mul2dsp to avoid unextend() | Eddie Hung | 2019-09-25 | 1 | -5/+4 | |
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| | | * | "abc_padding" attr for blackbox outputs that were padded, remove them later | Eddie Hung | 2019-09-23 | 1 | -3/+16 | |
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| | | * | Set [AB]CASCREG to legal values | Eddie Hung | 2019-09-23 | 1 | -6/+10 | |
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| | | * | Comment to explain separating CREG packing | Eddie Hung | 2019-09-23 | 1 | -0/+8 | |
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| | | * | Separate out CREG packing into new pattern, to avoid conflict with PREG | Eddie Hung | 2019-09-23 | 4 | -46/+273 | |
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index : iCE40/yosys | |
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