| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | Update docs with bullet points | Eddie Hung | 2019-11-26 | 1 | -10/+9 | |
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| | * | | | | Move \init from source wire to submod if output port | Eddie Hung | 2019-11-25 | 1 | -0/+7 | |
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| * | | | | | Fix submod -hidden | Eddie Hung | 2019-11-26 | 1 | -5/+6 | |
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| * | | | | | clkpart to use 'submod -hidden' | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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| * | | | | | Add -hidden option to submod | Eddie Hung | 2019-11-26 | 1 | -20/+40 | |
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| * | | | | | Fix debug | Eddie Hung | 2019-11-25 | 1 | -3/+3 | |
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| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 1 | -0/+41 | |
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| | * | | | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -0/+41 | |
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| * | | | | | abc9 to contain time call | Eddie Hung | 2019-11-25 | 1 | -1/+1 | |
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| * | | | | | abc9 to no longer to clock partitioning, operate on whole modules only | Eddie Hung | 2019-11-25 | 1 | -139/+32 | |
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| * | | | | | clkpart to analyse async flops too | Eddie Hung | 2019-11-25 | 1 | -0/+8 | |
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| * | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-23 | 1 | -2/+3 | |
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| | * | | | | | More oopsies | Eddie Hung | 2019-11-23 | 1 | -2/+3 | |
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| * | | | | | | Conditioning abc9 on POs not accurate due to cells | Eddie Hung | 2019-11-23 | 1 | -15/+6 | |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-23 | 1 | -13/+27 | |
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| | * | | | | | Print ".en=" only if there is an enable signal | Eddie Hung | 2019-11-23 | 1 | -1/+1 | |
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| | * | | | | | Escape IdStrings | Eddie Hung | 2019-11-23 | 1 | -3/+2 | |
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| | * | | | | | More sane naming of submod | Eddie Hung | 2019-11-23 | 1 | -2/+2 | |
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| | * | | | | | Add -set_attr option, -unpart to take attr name | Eddie Hung | 2019-11-23 | 1 | -10/+25 | |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-23 | 1 | -18/+34 | |
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| | * | | | | | Do not use log_signal() for empty SigSpec to prevent "{ }" | Eddie Hung | 2019-11-22 | 1 | -2/+4 | |
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| | * | | | | | Call submod once, more meaningful submod names, ignore largest domain | Eddie Hung | 2019-11-22 | 1 | -18/+32 | |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 3 | -1/+1 | |
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| | * | | | | | Move clkpart into passes/hierarchy | Eddie Hung | 2019-11-22 | 3 | -1/+1 | |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -48/+39 | |
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| | * | | | | | submod to bitty rather bussy, for bussy wires used as input and output | Eddie Hung | 2019-11-22 | 1 | -48/+39 | |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -2/+10 | |
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| | * | | | | | Constant driven signals are also an input to submodules | Eddie Hung | 2019-11-22 | 1 | -2/+10 | |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -1/+0 | |
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| | * | | | | | Oops | Eddie Hung | 2019-11-22 | 1 | -1/+0 | |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -8/+9 | |
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| | * | | | | | Only action if there is more than one clock domain | Eddie Hung | 2019-11-22 | 1 | -7/+8 | |
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| | * | | | | | Replace TODO | Eddie Hung | 2019-11-22 | 1 | -1/+1 | |
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| * | | | | | | Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -1/+19 | |
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| | * | | | | | sigmap(wire) should inherit port_output status of POs | Eddie Hung | 2019-11-22 | 1 | -1/+19 | |
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| * | | | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 2 | -1/+2 | |
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| | * | | | | Brackets | Eddie Hung | 2019-11-22 | 1 | -1/+1 | |
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| | * | | | | Entry in Makefile.inc | Eddie Hung | 2019-11-22 | 1 | -0/+1 | |
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| * | | | | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 5 | -4/+430 | |
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| | * | | | | New 'clkpart' to {,un}partition design according to clock/enable | Eddie Hung | 2019-11-22 | 1 | -0/+268 | |
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| | * | | | Add "opt_mem" pass | Clifford Wolf | 2019-11-22 | 3 | -0/+146 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage | David Shah | 2019-11-21 | 1 | -4/+16 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_ | Eddie Hung | 2019-11-21 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | Since they should be captured downwards from the owning flop | |||||
| * | | | | endomain -> ctrldomain | Eddie Hung | 2019-11-20 | 1 | -3/+3 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 14 | -182/+449 | |
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| | * | | | Fix #1462, #1480. | Marcin Kościelnicki | 2019-11-19 | 2 | -9/+11 | |
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| | * | | Fix #1496. | Marcin Kościelnicki | 2019-11-18 | 1 | -4/+8 | |
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| | * | | Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst | Clifford Wolf | 2019-11-17 | 1 | -4/+10 | |
| | |\ \ | | | | | | | | | wreduce: Don't trim zeros or sext when not matching ARST_VALUE | |||||
| | | * | | wreduce: Don't trim zeros or sext when not matching ARST_VALUE | David Shah | 2019-11-14 | 1 | -4/+10 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | Merge pull request #1490 from YosysHQ/clifford/autoname | Clifford Wolf | 2019-11-14 | 2 | -0/+135 | |
| | |\ \ \ | | |/ / | |/| | | Add "autoname" pass and use it in "synth_ice40" | |||||
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index : iCE40/yosys | |
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