| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | | * | | | | | | Ignore all 1'bx in (* init *) | Eddie Hung | 2019-08-27 | 1 | -3/+1 | |
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| | | | * | | | | | | In sat: 'x' in init attr should not override constant | Eddie Hung | 2019-08-22 | 1 | -0/+2 | |
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| | | * | | | | | | improve clkbuf_inhibit propagation upwards through hierarchy | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+12 | |
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| | | * | | | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 4 | -32/+279 | |
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| | | | * | | | | | | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 | |
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| | | | * | | | | | Fix port hanlding in pmgen | Clifford Wolf | 2019-08-23 | 1 | -4/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | | * | | | | | Add pmgen slices and choices | Clifford Wolf | 2019-08-23 | 4 | -28/+276 | |
| | | | |/ / / / | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | clkbufmap to only check clkbuf_inhibit if no selection given | Eddie Hung | 2019-08-23 | 1 | -5/+18 | |
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| | | * | | | | | Review comment from @cliffordwolf | Eddie Hung | 2019-08-23 | 1 | -1/+2 | |
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| | | * | | | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 48 | -768/+2262 | |
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| | | | * | | | | Spelling | Eddie Hung | 2019-08-22 | 1 | -2/+2 | |
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| | | | * | | | Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx | Eddie Hung | 2019-08-22 | 1 | -4/+26 | |
| | | | |\ \ \ | | | | |_|/ | | | |/| | | opt_expr to trim A port of $shiftx/$shift | |||||
| | | | | * | | Copy-paste typo | Eddie Hung | 2019-08-22 | 1 | -1/+1 | |
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| | | | | * | | Respect opt_expr -keepdc as per @cliffordwolf | Eddie Hung | 2019-08-22 | 1 | -1/+1 | |
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| | | | | * | | Handle $shift and Y_WIDTH > 1 as per @cliffordwolf | Eddie Hung | 2019-08-22 | 1 | -4/+8 | |
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| | | | | * | | Add cover() | Eddie Hung | 2019-08-22 | 1 | -0/+1 | |
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| | | | | * | | Canonical form | Eddie Hung | 2019-08-22 | 1 | -5/+5 | |
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| | | | | * | | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 | |
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| | | | * / | Fix test_pmgen deps | Miodrag Milanovic | 2019-08-21 | 1 | -1/+1 | |
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| | | | * | Merge pull request #1314 from YosysHQ/eddie/fix_techmap | Clifford Wolf | 2019-08-21 | 1 | -4/+6 | |
| | | | |\ | | | | | | | | | | | techmap -max_iter to apply to each module individually | |||||
| | | | | * | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| | | | | * | techmap -max_iter to apply to each module individually | Eddie Hung | 2019-08-20 | 1 | -4/+6 | |
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| | | | * | | Fix copy-paste typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 | |
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| | | * | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-16 | 41 | -2157/+2152 | |
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| | | * | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 2 | -28/+9 | |
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| | | * | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 2 | -29/+4 | |
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| | | * | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 3 | -20/+356 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | |||||
| * | | | | | Fix compile error | Eddie Hung | 2019-08-20 | 2 | -8/+14 | |
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| * | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-20 | 55 | -1644/+3111 | |
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| | * | | | | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 1 | -43/+80 | |
| | |\ \ \ \ | | | | | | | | | | | | | Refactor abc9 to use port attributes, not module attributes | |||||
| | | * | | | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -6/+6 | |
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| | | * | | | | Use ID() | Eddie Hung | 2019-08-16 | 1 | -3/+3 | |
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| | | * | | | | Compute abc_scc_break and move CI/CO outside of each abc9 | Eddie Hung | 2019-08-16 | 1 | -43/+80 | |
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| | * | | | | Merge branch 'master' into clifford/pmgen | Clifford Wolf | 2019-08-20 | 4 | -36/+33 | |
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| | | * \ \ \ | Merge pull request #1309 from whitequark/proc_clean-fix-1268 | whitequark | 2019-08-20 | 1 | -2/+1 | |
| | | |\ \ \ \ | | | | | | | | | | | | | | | proc_clean: fix order of switch insertion | |||||
| | | | * | | | | proc_clean: fix order of switch insertion. | whitequark | 2019-08-19 | 1 | -2/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1268. | |||||
| | | * | | | | | Fix typo | Eddie Hung | 2019-08-19 | 1 | -1/+1 | |
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| | | * | | | | | ID({A,B,Y}) -> ID::{A,B,Y} for opt_share.cc | Eddie Hung | 2019-08-19 | 1 | -30/+30 | |
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| | | * | | | | Ignore all generated headers for pmgen pass | Miodrag Milanovic | 2019-08-18 | 1 | -2/+1 | |
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| | * | | | | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen | Clifford Wolf | 2019-08-19 | 47 | -1514/+2270 | |
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| | | * | | | | Merge branch 'master' into eddie/pr1266_again | whitequark | 2019-08-18 | 44 | -2165/+2814 | |
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| | | | * \ \ \ | Merge pull request #1283 from YosysHQ/clifford/fix1255 | Clifford Wolf | 2019-08-17 | 2 | -2/+3 | |
| | | | |\ \ \ \ | | | | | | | | | | | | | | | | | Fix various NDEBUG compiler warnings | |||||
| | | | | * \ \ \ | Merge branch 'master' into clifford/fix1255 | Clifford Wolf | 2019-08-15 | 13 | -996/+1044 | |
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| | | | | * | | | | | Fix various NDEBUG compiler warnings, closes #1255 | Clifford Wolf | 2019-08-13 | 2 | -2/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | | * | | | | | | Merge pull request #1303 from YosysHQ/bogdanvuk/opt_share | Clifford Wolf | 2019-08-17 | 3 | -1/+655 | |
| | | | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | Implement opt_share from @bogdanvuk | |||||
| | | | | * | | | | | | Use ID() macro | Eddie Hung | 2019-08-16 | 1 | -118/+110 | |
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| | | | | * | | | | | | Add 'opt_share' to 'opt -full' | Eddie Hung | 2019-08-16 | 1 | -0/+5 | |
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| | | | | * | | | | | | Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_share | Eddie Hung | 2019-08-16 | 2 | -1/+658 | |
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| | | | | | * | | | | | Fix wrong results when opt_share called before opt_clean | Bogdan Vukobratovic | 2019-08-07 | 1 | -18/+14 | |
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| | | | | | * | | | | | Support various binary operators in opt_share | Bogdan Vukobratovic | 2019-08-04 | 1 | -194/+392 | |
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