| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | | Support unregistered cascades for A and B inputs | Eddie Hung | 2019-12-23 | 1 | -47/+74 | |
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| | * | | | | Add DSP48A* PCOUT -> PCIN cascade support | Eddie Hung | 2019-12-23 | 1 | -10/+10 | |
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| | * | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | Marcin Kościelnicki | 2019-12-22 | 4 | -11/+886 | |
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| * | | | | | Add "synth_xilinx -dff" option, cleanup abc9 | Eddie Hung | 2019-12-30 | 1 | -49/+19 | |
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| * | | | | | Grammar | Eddie Hung | 2019-12-30 | 1 | -1/+1 | |
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| * | | | | | Disable clock domain partitioning in Yosys pass, let ABC do it | Eddie Hung | 2019-12-23 | 1 | -6/+22 | |
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| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-20 | 2 | -20/+19 | |
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| | * | | | | Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut | Eddie Hung | 2019-12-20 | 1 | -19/+18 | |
| | |\ \ \ \ | | | | | | | | | | | | | Interpret "abc9 -lut" as lut string only if [0-9:] | |||||
| | | * | | | | Interpret "abc9 -lut" as lut string only if [0-9:] | Eddie Hung | 2019-12-18 | 1 | -19/+18 | |
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| | * | | | | | Merge pull request #1581 from YosysHQ/clifford/fix1565 | Eddie Hung | 2019-12-19 | 1 | -1/+1 | |
| | |\ \ \ \ \ | | |/ / / / | |/| | | | | Fix sim for assignments with lhs<rhs size | |||||
| | | * | | | | Fix sim for assignments with lhs<rhs size, fixes #1565 | Clifford Wolf | 2019-12-17 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t | Eddie Hung | 2019-12-19 | 1 | -5/+5 | |
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| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-19 | 5 | -4/+245 | |
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| | * | | | | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-12-18 | 3 | -2/+147 | |
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| | | * \ \ \ \ | Merge pull request #1572 from nakengelhardt/scratchpad_pass | Eddie Hung | 2019-12-18 | 2 | -0/+131 | |
| | | |\ \ \ \ \ | | | | | | | | | | | | | | | | | add a command to read/modify scratchpad contents | |||||
| | | | * | | | | | use extra_args | N. Engelhardt | 2019-12-18 | 1 | -1/+1 | |
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| | | | * | | | | | add assert option to scratchpad command | N. Engelhardt | 2019-12-16 | 1 | -5/+44 | |
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| | | | * | | | | | add periods and newlines to help message | N. Engelhardt | 2019-12-13 | 1 | -5/+5 | |
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| | | | * | | | | | add test and make help message more verbose | N. Engelhardt | 2019-12-12 | 1 | -1/+6 | |
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| | | | * | | | | | add a command to read/modify scratchpad contents | N. Engelhardt | 2019-12-12 | 2 | -0/+87 | |
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| | | * | | | | | xilinx: Add xilinx_dffopt pass (#1557) | Marcin Kościelnicki | 2019-12-18 | 1 | -2/+16 | |
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| | * / | | | | Cleanup | Eddie Hung | 2019-12-17 | 1 | -11/+7 | |
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| | * | | | | Enforce non-existence | Eddie Hung | 2019-12-16 | 1 | -0/+4 | |
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| | * | | | | Update doc | Eddie Hung | 2019-12-16 | 1 | -4/+6 | |
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| | * | | | | More sloppiness, thanks @dh73 for spotting | Eddie Hung | 2019-12-16 | 1 | -4/+4 | |
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| | * | | | | Oops | Eddie Hung | 2019-12-16 | 1 | -4/+1 | |
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| | * | | | | Implement 'attributes' grammar | Eddie Hung | 2019-12-16 | 1 | -80/+88 | |
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| | * | | | | Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattr | Eddie Hung | 2019-12-16 | 1 | -1/+90 | |
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| | | * | | | | Fixing compiler warning/issues. Moving test script to the correct place | Diego H | 2019-12-16 | 1 | -8/+8 | |
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| | | * | | | | Merging attribute rules into a single match block; Adding tests | Diego H | 2019-12-15 | 1 | -68/+80 | |
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| | | * | | | | Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific | Diego H | 2019-12-13 | 1 | -0/+77 | |
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| | * / / / | Fix opt_expr.eqneq.cmpzero debug print | Alyssa Milburn | 2019-12-15 | 1 | -1/+1 | |
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| * | | | | Remove &verify -s | Eddie Hung | 2019-12-17 | 1 | -1/+1 | |
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| * | | | | Use pool<> instead of std::set<> to preserver ordering | Eddie Hung | 2019-12-17 | 1 | -6/+6 | |
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| * | | | | Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop | Eddie Hung | 2019-12-16 | 1 | -5/+27 | |
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| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-12 | 1 | -8/+67 | |
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| | * | | | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr | Eddie Hung | 2019-12-09 | 1 | -8/+67 | |
| | |\ \ \ | | | | | | | | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER | |||||
| | | * | | | ice40_wrapcarry -unwrap to preserve 'src' attribute | Eddie Hung | 2019-12-09 | 1 | -1/+9 | |
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| | | * | | | -unwrap to create $lut not SB_LUT4 for opt_lut | Eddie Hung | 2019-12-09 | 1 | -7/+5 | |
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| | | * | | | Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4 | Eddie Hung | 2019-12-09 | 1 | -7/+11 | |
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| | | * | | | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 1 | -17/+55 | |
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| | | * | | | Drop keep=0 attributes on SB_CARRY | Eddie Hung | 2019-12-06 | 1 | -0/+8 | |
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| | | * | | | Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-12-05 | 1 | -0/+1 | |
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| | | * | | | ice40_wrapcarry to preserve SB_CARRY's attributes | Eddie Hung | 2019-12-03 | 1 | -0/+2 | |
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| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-12-06 | 2 | -175/+137 | |
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| | * | | | | iopadmap: Refactor and fix tristate buffer mapping. (#1527) | Marcin Kościelnicki | 2019-12-04 | 1 | -146/+97 | |
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not). | |||||
| | * | | | abc9: Fix breaking of SCCs | David Shah | 2019-12-01 | 1 | -29/+40 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | Call abc9 with "&write -n", and parse_xaiger() to cope | Eddie Hung | 2019-12-06 | 1 | -2/+2 | |
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| * | | | | Fix abc9 re-integration, remove abc9_control_wire, use cell->type as | Eddie Hung | 2019-12-06 | 1 | -39/+15 | |
| | | | | | | | | | | | | | | | | | as part of clock domain for mergeability class | |||||
| * | | | | abc9 to do clock partitioning again | Eddie Hung | 2019-12-05 | 1 | -37/+144 | |
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index : iCE40/yosys | |
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