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| | * | | Error detection for co-simulationMiodrag Milanovic2022-02-041-0/+3
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| | * | | bug fix and cleanupsMiodrag Milanovic2022-02-041-5/+5
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| | * | | respect hide_internal flagMiodrag Milanovic2022-02-021-1/+1
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| | * | | unify cycles counting and cleanupMiodrag Milanovic2022-02-021-36/+35
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| | * | | added stimulus mode and param checkMiodrag Milanovic2022-02-021-5/+31
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| | * | | error when no signal foundMiodrag Milanovic2022-01-311-0/+2
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| | * | | CleanupMiodrag Milanovic2022-01-311-1/+1
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| | * | | Compare bits when not all are definedMiodrag Milanovic2022-01-311-3/+17
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| | * | | CleanupMiodrag Milanovic2022-01-311-2/+2
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| | * | | message updateMiodrag Milanovic2022-01-311-1/+1
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| | * | | Display simulation time dataMiodrag Milanovic2022-01-311-1/+4
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| | * | | Use edges when explicitMiodrag Milanovic2022-01-311-1/+5
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| | * | | Updating initial state and checksMiodrag Milanovic2022-01-311-15/+28
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| | * | | Fix scopeMiodrag Milanovic2022-01-311-1/+1
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| | * | | check if stop before startMiodrag Milanovic2022-01-281-0/+3
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| | * | | set initial state, only flip-flopsMiodrag Milanovic2022-01-281-1/+28
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| | * | | ignore not found private signalsMiodrag Milanovic2022-01-281-0/+3
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| | * | | recursive checkMiodrag Milanovic2022-01-281-26/+34
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| | * | | Do actual compareMiodrag Milanovic2022-01-281-5/+16
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| | * | | Add more options and time handlingMiodrag Milanovic2022-01-281-2/+103
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| | * | | Display values of outputsMiodrag Milanovic2022-01-261-12/+10
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| | * | | Check if stimulatedMiodrag Milanovic2022-01-261-0/+14
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| | * | | Read fst and use data to set inputsMiodrag Milanovic2022-01-261-10/+92
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| | * | | Add ability to write to FST fileMiodrag Milanovic2022-01-261-11/+109
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| * | | Correct a typo in the manualYRabbit2022-02-021-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * | | Update commentScott Thibault2022-02-021-1/+1
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| * | | Fix unextend method for signed constantsScott Thibault2022-02-021-2/+1
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| * | | opt_reduce: Add $bmux and $demux optimization patterns.Marcelina Kościelnicka2022-01-301-60/+337
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| * | | Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-288-3/+239
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| * | | opt_dff: Don't mutate muxes while ModWalker is active.Marcelina Kościelnicka2022-01-281-98/+112
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| * | | memory_bram: Make use of new mem emulation functions to map more RAMs.Marcelina Kościelnicka2022-01-271-18/+10
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| * | opt_dff: fix sequence point copy paste bugAustin Seipp2022-01-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer GCCs emit the following warning for opt_dff: passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point] 560 | ff.has_clk = ff.has_ce = ff.has_clk = false; | ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Which is correct: the order of whether the read or write of has_clk occurs first is undefined since there is no sequence point between them. This is almost certainly just a typo/copy paste error and objectively wrong, so just fix it. Signed-off-by: Austin Seipp <aseipp@pobox.com>
| * | memory_share: Fix SAT-based sharing for wide ports.Marcelina Kościelnicka2021-12-201-1/+3
| | | | | | | | | | | | Fixes #3117.
| * | bugpoint: avoid infinite loop between -connections and -wires.Catherine2021-12-151-1/+1
| | | | | | | | | | | | Fixes #3113.
| * | Add clean_zerowidth pass, use it for Verilog output.Marcelina Kościelnicka2021-12-122-1/+212
| | | | | | | | | | | | | | | | | | | | | This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103.
| * | opt_mem_priority: Fix non-ascii char in help message.Marcelina Kościelnicka2021-12-091-1/+1
| | | | | | | | | | | | This is a fixed version of #3072.
| * | sta: very crude static timing analysis passLofty2021-11-253-30/+341
| | | | | | | | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
| * | show: Fix wire bit indexing.Marcelina Kościelnicka2021-11-121-3/+16
| | | | | | | | | | | | Fixes #3078.
| * | Merge pull request #3077 from YosysHQ/claire/genlibClaire Xen2021-11-101-21/+40
| |\ \ | | | | | | | | Add genlib support to ABC command
| | * | Spelling fix in abc.ccClaire Xen2021-11-101-1/+1
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| | * | Add genlib support to ABC commandClaire Xenia Wolf2021-11-101-21/+40
| | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * | | iopadmap: Fix ebmarassing typoMarcelina Kościelnicka2021-11-101-1/+1
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| * | | iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-091-7/+22
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| * | | gowin: widelut support (#3042)Pepijn de Vos2021-11-061-2/+8
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| * | Make it work on allMiodrag Milanovic2021-11-051-2/+4
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| * | Correct way of setting maybe_unsused on labelsMiodrag Milanovic2021-11-051-4/+2
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| * | flatten: Keep sigmap around between flatten_cell invocations.Marcelina Kościelnicka2021-11-021-3/+4
| | | | | | | | | | | | Fixes #3064.
| * | proc_dff: Emit $aldff.Marcelina Kościelnicka2021-10-271-32/+7
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| * | dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-271-973/+889
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| * | verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-252-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
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