| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix missing newline at end of file | Clifford Wolf | 2019-08-22 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Proper arith for Anlogic and use standard pass | Miodrag Milanovic | 2019-08-12 | 1 | -17/+25 |
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| * | anlogic : Fix alu mapping | Miodrag Milanovic | 2019-08-03 | 1 | -16/+8 |
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| * | Initial support for Anlogic FPGA | Miodrag Milanovic | 2018-12-01 | 1 | -0/+84 |
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index : iCE40/yosys | |
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