aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/anlogic/synth_anlogic.cc
Commit message (Collapse)AuthorAgeFilesLines
* anlogic: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-12/+10
|
* anlogic: support BRAM mappingIcenowy Zheng2021-12-171-1/+17
| | | | | | | | | | | Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-2/+2
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-141-1/+1
|
* Use C++11 final/override keywords.whitequark2020-06-181-4/+4
|
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
|
* Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-021-6/+18
|\ | | | | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| * Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-011-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
* | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
| |
* | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
|/ | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* Proper arith for Anlogic and use standard passMiodrag Milanovic2019-08-121-1/+6
|
* Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-021-0/+1
|\ | | | | anlogic: implement DRAM initialization
| * anlogic: implement DRAM initializationIcenowy Zheng2018-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-021-0/+1
|\ \ | | | | | | Initialization of Anlogic DFFs
| * | anlogic: set the init value of DFFsIcenowy Zheng2018-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As dffinit has already supported for different initialization strings for DFFs and check for re-initialization, initialization of Anlogic DFFs are now ready to go. Support for set the init values of Anlogic DFFs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* | Anlogic: let LUT5/6 have more cost than LUT4-Icenowy Zheng2018-12-191-1/+1
|/ | | | | | | | | | | | | | According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s. So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost 2x resource of a LUT5. Change the -lut parameter passed to the abc command to pass this cost info to the ABC process. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* anlogic: add support for Eagle Distributed RAMIcenowy Zheng2018-12-171-0/+6
| | | | | | | | | | | | | The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Initial support for Anlogic FPGAMiodrag Milanovic2018-12-011-0/+205
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-03 18:11:19 +0000