| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -3/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -0/+28 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵ | Clifford Wolf | 2019-04-23 | 1 | -70/+70 |
| | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $specify2 and $specify3 cells to simlib | Clifford Wolf | 2019-04-23 | 1 | -0/+147 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -0/+24 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -0/+16 |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+8 |
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| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -0/+12 |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 1 | -2/+6 |
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| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 1 | -0/+13 |
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| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 1 | -12/+0 |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -8/+0 |
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| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 1 | -0/+24 |
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| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 1 | -0/+17 |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -9/+1 |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -0/+16 |
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| * | Improved support for $sop cells | Clifford Wolf | 2016-06-17 | 1 | -3/+3 |
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| * | Added $sop cell type and "abc -sop" | Clifford Wolf | 2016-06-17 | 1 | -0/+28 |
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| * | Added more cell help messages | Clifford Wolf | 2016-03-29 | 1 | -0/+73 |
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| * | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 1 | -4/+5 |
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| * | Added $tribuf and $_TBUF_ sim models | Clifford Wolf | 2015-08-16 | 1 | -0/+14 |
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| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -2/+2 |
| | | | | | Smaller this time | ||||
| * | Added WORDS parameter to $meminit | Clifford Wolf | 2015-07-31 | 1 | -1/+2 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
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| * | make all vector-size related integer params in $mem sim model signed | Clifford Wolf | 2015-04-05 | 1 | -6/+6 |
| | | | | | | | this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory. | ||||
| * | Added $assume cell type | Clifford Wolf | 2015-02-26 | 1 | -1/+18 |
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| * | Smaller default parameters in $mem simlib model | Clifford Wolf | 2015-02-15 | 1 | -2/+2 |
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| * | Added $meminit support to "memory" command | Clifford Wolf | 2015-02-14 | 1 | -3/+15 |
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| * | Added $meminit cell type | Clifford Wolf | 2015-02-14 | 1 | -0/+22 |
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| * | Some test related fixes | Clifford Wolf | 2015-02-12 | 1 | -4/+4 |
| | | | | | (incl. removal of three bad test cases) | ||||
| * | Added $equiv cell type | Clifford Wolf | 2015-01-19 | 1 | -1/+23 |
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| * | Progress in memory_bram | Clifford Wolf | 2015-01-03 | 1 | -0/+3 |
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| * | Added proper clkpol support to memory_bram | Clifford Wolf | 2015-01-02 | 1 | -1/+1 |
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| * | New $mem simlib model | Clifford Wolf | 2015-01-02 | 1 | -95/+36 |
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| * | Fixed simlib entries for $memrd and $memwr | Clifford Wolf | 2014-12-30 | 1 | -0/+2 |
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| * | Added $dffe cell type | Clifford Wolf | 2014-12-08 | 1 | -0/+19 |
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| * | Fixed $macc simlib model for zero-config | Clifford Wolf | 2014-09-16 | 1 | -1/+1 |
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| * | Fixed simlib $macc model for xilinx xsim | Clifford Wolf | 2014-09-08 | 1 | -1/+15 |
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| * | Simplified $fa undef model | Clifford Wolf | 2014-09-08 | 1 | -1/+1 |
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| * | Fixes and cleanups for blackbox.v | Clifford Wolf | 2014-09-08 | 1 | -68/+70 |
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| * | Added $lcu cell type | Clifford Wolf | 2014-09-08 | 1 | -0/+23 |
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| * | Added "$fa" cell type | Clifford Wolf | 2014-09-08 | 1 | -0/+16 |
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| * | Various bug fixes (related to $macc model testing) | Clifford Wolf | 2014-09-06 | 1 | -1/+1 |
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| * | Added $macc SAT model | Clifford Wolf | 2014-09-06 | 1 | -3/+3 |
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| * | Added $macc simlib model (also use as techmap rule for now) | Clifford Wolf | 2014-09-06 | 1 | -0/+86 |
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| * | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 1 | -24/+0 |
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| * | Undef-related fixes in simlib $alu model | Clifford Wolf | 2014-09-02 | 1 | -3/+6 |
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| * | Small bug fixes in $not, $neg, and $shiftx models | Clifford Wolf | 2014-09-02 | 1 | -3/+2 |
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| * | Fixed "test_cell -simlib all" | Clifford Wolf | 2014-09-01 | 1 | -2/+3 |
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