| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add $aldff and $aldffe: flip-flops with async load. | Marcelina Kościelnicka | 2021-10-02 | 1 | -0/+49 |
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| * | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 1 | -0/+169 |
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| * | memory: Introduce $meminit_v2 cell, with EN input. | Marcelina Kościelnicka | 2021-07-28 | 1 | -0/+24 |
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| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
| | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g; | ||||
| * | Fix some trivial typos. | Tom Verbeure | 2021-01-03 | 1 | -5/+5 |
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| * | Respect \A_SIGNED for $shift | Xiretza | 2020-08-18 | 1 | -4/+12 |
| | | | | | | | This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits). | ||||
| * | Add new builtin FF types | Marcelina Kościelnicka | 2020-06-23 | 1 | -0/+156 |
| | | | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits). | ||||
| * | Add flooring division operator | Xiretza | 2020-05-28 | 1 | -0/+43 |
| | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor. | ||||
| * | Add flooring modulo operator | Xiretza | 2020-05-28 | 1 | -0/+48 |
| | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor. | ||||
| * | Fix the truth table for $_SR_* cells. | Marcelina Kościelnicka | 2020-04-15 | 1 | -1/+1 |
| | | | | | | | | | This brings the documented behavior for these cells in line with $_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S. The models were already reflecting that behavior. Also get rid of sim-synth mismatch in the models while we're at it. | ||||
| * | Reformat so it shows up/looks nice when "help $alu" and "help $alu+" | Eddie Hung | 2019-08-09 | 1 | -25/+34 |
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| * | A bit more on where $lcu comes from | Eddie Hung | 2019-08-09 | 1 | -0/+2 |
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| * | Add more comments | Eddie Hung | 2019-08-09 | 1 | -4/+18 |
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| * | Add a few comments to document $alu and $lcu | Eddie Hung | 2019-08-08 | 1 | -9/+12 |
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| * | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -3/+4 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -0/+28 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵ | Clifford Wolf | 2019-04-23 | 1 | -70/+70 |
| | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $specify2 and $specify3 cells to simlib | Clifford Wolf | 2019-04-23 | 1 | -0/+147 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -0/+24 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add $live and $fair cell types, add support for s_eventually keyword | Clifford Wolf | 2017-02-25 | 1 | -0/+16 |
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| * | Add $cover cell type and SVA cover() support | Clifford Wolf | 2017-02-04 | 1 | -0/+8 |
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| * | Added $anyseq cell type | Clifford Wolf | 2016-10-14 | 1 | -0/+12 |
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| * | Added $global_clock verilog syntax support for creating $ff cells | Clifford Wolf | 2016-10-14 | 1 | -2/+6 |
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| * | Added $ff and $_FF_ cell types | Clifford Wolf | 2016-10-12 | 1 | -0/+13 |
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| * | Removed $aconst cell type | Clifford Wolf | 2016-08-30 | 1 | -12/+0 |
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| * | Removed $predict again | Clifford Wolf | 2016-08-28 | 1 | -8/+0 |
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| * | Added $anyconst and $aconst | Clifford Wolf | 2016-07-27 | 1 | -0/+24 |
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| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 1 | -0/+17 |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 1 | -9/+1 |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 1 | -0/+16 |
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| * | Improved support for $sop cells | Clifford Wolf | 2016-06-17 | 1 | -3/+3 |
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| * | Added $sop cell type and "abc -sop" | Clifford Wolf | 2016-06-17 | 1 | -0/+28 |
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| * | Added more cell help messages | Clifford Wolf | 2016-03-29 | 1 | -0/+73 |
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| * | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 1 | -4/+5 |
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| * | Added $tribuf and $_TBUF_ sim models | Clifford Wolf | 2015-08-16 | 1 | -0/+14 |
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| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -2/+2 |
| | | | | | Smaller this time | ||||
| * | Added WORDS parameter to $meminit | Clifford Wolf | 2015-07-31 | 1 | -1/+2 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
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| * | make all vector-size related integer params in $mem sim model signed | Clifford Wolf | 2015-04-05 | 1 | -6/+6 |
| | | | | | | | this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory. | ||||
| * | Added $assume cell type | Clifford Wolf | 2015-02-26 | 1 | -1/+18 |
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| * | Smaller default parameters in $mem simlib model | Clifford Wolf | 2015-02-15 | 1 | -2/+2 |
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| * | Added $meminit support to "memory" command | Clifford Wolf | 2015-02-14 | 1 | -3/+15 |
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| * | Added $meminit cell type | Clifford Wolf | 2015-02-14 | 1 | -0/+22 |
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| * | Some test related fixes | Clifford Wolf | 2015-02-12 | 1 | -4/+4 |
| | | | | | (incl. removal of three bad test cases) | ||||
| * | Added $equiv cell type | Clifford Wolf | 2015-01-19 | 1 | -1/+23 |
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| * | Progress in memory_bram | Clifford Wolf | 2015-01-03 | 1 | -0/+3 |
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| * | Added proper clkpol support to memory_bram | Clifford Wolf | 2015-01-02 | 1 | -1/+1 |
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| * | New $mem simlib model | Clifford Wolf | 2015-01-02 | 1 | -95/+36 |
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| * | Fixed simlib entries for $memrd and $memwr | Clifford Wolf | 2014-12-30 | 1 | -0/+2 |
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