| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Added support for non-const === and !== (for miter circuits) | Clifford Wolf | 2013-12-27 | 1 | -0/+36 | |
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| * | Renamed stdcells_sim.v to simcells.v and fixed blackbox.v | Clifford Wolf | 2013-11-24 | 1 | -8/+8 | |
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| * | Cleanups and bugfixes in response to new internal cell checker | Clifford Wolf | 2013-11-11 | 1 | -6/+7 | |
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| * | Added $sr, $dffsr and $dlatch cell types | Clifford Wolf | 2013-10-18 | 1 | -20/+76 | |
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| * | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 | 1 | -0/+944 | |
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index : iCE40/yosys | |
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