| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | techmap: fix shiftx2mux decomposition | Eddie Hung | 2020-02-07 | 1 | -8/+6 |
| | | |||||
| * | shiftx2mux: fix select out of bounds | Eddie Hung | 2020-02-05 | 1 | -1/+2 |
| | | |||||
| * | Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux | Eddie Hung | 2020-02-05 | 2 | -2/+0 |
| |\ | |||||
| | * | abc9_ops: -write_box is empty, output a dummy box to prevent ABC error | Eddie Hung | 2020-01-15 | 2 | -2/+0 |
| | | | |||||
| * | | Explicitly create separate $mux cells | Eddie Hung | 2020-01-21 | 1 | -2/+2 |
| | | | |||||
| * | | Fix tests -- when Y_WIDTH is non-pow-2 | Eddie Hung | 2020-01-21 | 1 | -3/+4 |
| | | | |||||
| * | | Move from +/shiftx2mux.v into +/techmap.v; cleanup | Eddie Hung | 2020-01-21 | 3 | -73/+69 |
| | | | |||||
| * | | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABC | Eddie Hung | 2020-01-21 | 2 | -0/+39 |
| |/ | |||||
| * | Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp | Clifford Wolf | 2019-11-11 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Makefile: don't assume python is called `python3` | Sean Cross | 2019-10-19 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io> | ||||
| * | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 |
| | | |||||
| * | Stop trying to be too smart by prematurely optimising | Eddie Hung | 2019-09-26 | 1 | -34/+6 |
| | | |||||
| * | mul2dsp.v slice names | Eddie Hung | 2019-09-25 | 1 | -5/+5 |
| | | |||||
| * | Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicit | Eddie Hung | 2019-09-25 | 1 | -3/+1 |
| | | |||||
| * | Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul" | Eddie Hung | 2019-09-25 | 1 | -2/+6 |
| | | | | | This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1. | ||||
| * | Revert "No need for $__mul anymore?" | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
| | | | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827. | ||||
| * | Remove _TECHMAP_CELLTYPE_ check since all $mul | Eddie Hung | 2019-09-25 | 1 | -6/+2 |
| | | |||||
| * | No need for $__mul anymore? | Eddie Hung | 2019-09-25 | 1 | -8/+8 |
| | | |||||
| * | Fix signedness bug | Eddie Hung | 2019-09-20 | 1 | -2/+2 |
| | | |||||
| * | Be sensitive to signedness | Eddie Hung | 2019-09-10 | 1 | -20/+21 |
| | | |||||
| * | Really get rid of 'opt_expr -fine' by being explicit | Eddie Hung | 2019-09-10 | 1 | -6/+33 |
| | | |||||
| * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-09-05 | 2 | -0/+2 |
| |\ | |||||
| | * | Use a dummy box file if none specified | Eddie Hung | 2019-08-28 | 2 | -0/+2 |
| | | | |||||
| * | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-08-30 | 1 | -1/+1 |
| |\ \ | |||||
| | * | | Merge branch 'master' into xc7dsp | David Shah | 2019-08-30 | 1 | -1/+1 |
| | |\| | |||||
| | | * | Missing newline | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
| | | | | |||||
| * | | | Only swap ports if $mul and not $__mul | Eddie Hung | 2019-08-13 | 1 | -1/+1 |
| | | | | |||||
| * | | | Add DSP_A_MAXWIDTH_PARTIAL, refactor | Eddie Hung | 2019-08-13 | 1 | -144/+110 |
| |/ / | |||||
| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 1 | -8/+36 |
| |\| | |||||
| | * | Reformat so it shows up/looks nice when "help $alu" and "help $alu+" | Eddie Hung | 2019-08-09 | 1 | -25/+34 |
| | | | |||||
| | * | A bit more on where $lcu comes from | Eddie Hung | 2019-08-09 | 1 | -0/+2 |
| | | | |||||
| | * | Add more comments | Eddie Hung | 2019-08-09 | 1 | -4/+18 |
| | | | |||||
| | * | Add a few comments to document $alu and $lcu | Eddie Hung | 2019-08-08 | 1 | -9/+12 |
| | | | |||||
| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-07 | 1 | -0/+19 |
| |\| | |||||
| | * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -0/+19 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Trim Y_WIDTH | Eddie Hung | 2019-08-01 | 1 | -5/+3 |
| | | | |||||
| * | | Add DSP_SIGNEDONLY back | Eddie Hung | 2019-08-01 | 1 | -0/+16 |
| | | | |||||
| * | | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH | Eddie Hung | 2019-08-01 | 1 | -4/+11 |
| | | | |||||
| * | | Revert "Do not do sign extension in techmap; let packer do it" | Eddie Hung | 2019-08-01 | 1 | -5/+14 |
| | | | | | | | | | This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd. | ||||
| * | | Fix B_WIDTH > DSP_B_MAXWIDTH case | Eddie Hung | 2019-08-01 | 1 | -32/+14 |
| | | | |||||
| * | | Do not compute sign bit if result is zero | Eddie Hung | 2019-07-31 | 1 | -1/+2 |
| | | | |||||
| * | | For signed multipliers, compute sign bit separately... | Eddie Hung | 2019-07-31 | 1 | -23/+42 |
| | | | |||||
| * | | Fix spacing | Eddie Hung | 2019-07-26 | 1 | -3/+3 |
| | | | |||||
| * | | Add copyright header, comment on cascade | Eddie Hung | 2019-07-24 | 1 | -4/+34 |
| | | | |||||
| * | | Typo for Y_WIDTH | Eddie Hung | 2019-07-23 | 1 | -1/+1 |
| | | | |||||
| * | | Use minimum sized width wires | Eddie Hung | 2019-07-22 | 1 | -7/+13 |
| | | | |||||
| * | | Indirection via $__soft_mul | Eddie Hung | 2019-07-19 | 1 | -9/+9 |
| | | | |||||
| * | | Do not do sign extension in techmap; let packer do it | Eddie Hung | 2019-07-19 | 1 | -14/+5 |
| | | | |||||
| * | | Do not $mul -> $__mul if A and B are less than maxwidth | Eddie Hung | 2019-07-19 | 1 | -1/+3 |
| | | | |||||
| * | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too | Eddie Hung | 2019-07-19 | 1 | -28/+68 |
| | | | |||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |