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* abc9_ops/xaiger: further reducing Module::derive() calls by ...Eddie Hung2020-05-142-7/+5
| | | | replacing _all_ (* abc9_box *) instantiations with their derived types
* Cleanup; reduce Module::derive() callsEddie Hung2020-05-142-4/+4
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* abc9: only do +/abc9_map if `DFFEddie Hung2020-05-141-0/+2
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* abc9: not enough to techmap_fail on (* init=1 *), hide them using $__Eddie Hung2020-05-142-10/+26
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* abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ tooEddie Hung2020-05-144-0/+55
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* abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxesEddie Hung2020-05-141-3/+0
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* techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-052-7/+30
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* Fix the truth table for $_SR_* cells.Marcelina Kościelnicka2020-04-153-26/+21
| | | | | | | | This brings the documented behavior for these cells in line with $_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S. The models were already reflecting that behavior. Also get rid of sim-synth mismatch in the models while we're at it.
* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-034-11/+120
|\ | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
| * cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmpEddie Hung2020-04-031-1/+1
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| * cmp2lcu: fail if `LUT_WIDTH < 2Eddie Hung2020-04-031-1/+1
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| * synth: only techmap cmp2{lut,lcu} if -lutEddie Hung2020-04-031-1/+1
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| * synth: use +/cmp2lcu.v in generic 'synth' tooEddie Hung2020-04-031-2/+2
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| * Cleanup +/cmp2lut.vEddie Hung2020-04-031-8/+0
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| * +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-33/+42
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| * Refactor +/cmp2lcu.v into recursive techmapEddie Hung2020-04-031-38/+65
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| * CleanupEddie Hung2020-04-031-31/+28
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| * Cleanup cmp2lcu.vEddie Hung2020-04-031-16/+16
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| * techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcuEddie Hung2020-04-032-0/+84
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| * cmp2lut: comment out unused since 362f4f9Eddie Hung2020-04-031-8/+8
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* | simcells.v: Generate the fine FF cell types by a python script.Marcin Kościelnicki2020-04-022-19/+270
|/ | | | | | This makes adding more FF types in the future much more manageable. Fixes #1824.
* Fix invalid verilog syntaxMiodrag Milanovic2020-03-141-1/+1
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* Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-031-2/+17
|\ | | | | Add -flowmap option to `synth{,_ice40}`
| * Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-281-2/+17
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* | Create +/abc9_model.v for $__ABC9_{DELAY,FF_}Eddie Hung2020-02-272-0/+11
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* techmap: fix shiftx2mux decompositionEddie Hung2020-02-071-8/+6
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* shiftx2mux: fix select out of boundsEddie Hung2020-02-051-1/+2
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* Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-052-2/+0
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| * abc9_ops: -write_box is empty, output a dummy box to prevent ABC errorEddie Hung2020-01-152-2/+0
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* | Explicitly create separate $mux cellsEddie Hung2020-01-211-2/+2
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* | Fix tests -- when Y_WIDTH is non-pow-2Eddie Hung2020-01-211-3/+4
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* | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-213-73/+69
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* | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-212-0/+39
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* Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Makefile: don't assume python is called `python3`Sean Cross2019-10-191-2/+2
| | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
* Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
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* Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-261-34/+6
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* mul2dsp.v slice namesEddie Hung2019-09-251-5/+5
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* Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicitEddie Hung2019-09-251-3/+1
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* Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"Eddie Hung2019-09-251-2/+6
| | | | This reverts commit 234738b103d4f2b3d937ed928fd89bc4e31627f1.
* Revert "No need for $__mul anymore?"Eddie Hung2019-09-251-8/+8
| | | | This reverts commit 1d875ac76a354f654f28b9632d83f6b43542e827.
* Remove _TECHMAP_CELLTYPE_ check since all $mulEddie Hung2019-09-251-6/+2
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* No need for $__mul anymore?Eddie Hung2019-09-251-8/+8
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* Fix signedness bugEddie Hung2019-09-201-2/+2
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* Be sensitive to signednessEddie Hung2019-09-101-20/+21
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* Really get rid of 'opt_expr -fine' by being explicitEddie Hung2019-09-101-6/+33
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* Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-052-0/+2
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| * Use a dummy box file if none specifiedEddie Hung2019-08-282-0/+2
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* | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-301-1/+1
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| * | Merge branch 'master' into xc7dspDavid Shah2019-08-301-1/+1
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