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* Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-093-3/+3
| | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-083-4/+4
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.Adam Greig2021-05-121-0/+22
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* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-11/+15
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* ecp5: Use dfflegalize.Marcelina Kościelnicka2020-07-054-254/+96
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-232-31/+31
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* Use C++11 final/override keywords.whitequark2020-06-183-9/+9
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* ecp5: cleanup unused +/ecp5/abc9_model.vEddie Hung2020-05-233-14/+0
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-0/+11
| | | | Fixes #2058.
* ecp5: latches_map.v if *not* -asyncprldEddie Hung2020-05-141-2/+2
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* ecp5: synth_ecp5 to no longer need +/ecp5/abc9_{,un}map.vEddie Hung2020-05-144-43/+3
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* ecp5: fix rebase mistakeEddie Hung2020-05-141-3/+3
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* ecp5: TRELLIS_FF bypass path only in async modeEddie Hung2020-05-141-8/+8
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* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-1/+1
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* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-3/+26
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* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-1/+1
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
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* Revert "ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-init"Eddie Hung2020-05-143-220/+64
| | | | This reverts commit 8c702b6cc0221a00021a3e4661c883bb591c924b.
* ecp5: (* abc9_flop *) gated behind YOSYSEddie Hung2020-05-141-0/+2
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* ecp5: add synth_ecp5 -dff to work with -abc9Eddie Hung2020-05-142-12/+47
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* ecp5: replace ecp5_ffinit with techmap rules + dff2dffs -match-initEddie Hung2020-05-143-64/+220
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* ecp5: Add missing SERDES parametersDavid Shah2020-05-121-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-0/+13
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* gowin,ecp5: remove generated files in `make clean`.whitequark2020-04-241-0/+9
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* ecp5: ecp5_gsr to skip cells that don't have GSR parameter againEddie Hung2020-04-221-1/+1
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* Cleanup use of hard-coded default parameters in light of #1945Eddie Hung2020-04-222-12/+6
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* ecp5: Force SIGNED ports to be 1 bitDavid Shah2020-04-161-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-103-1/+74
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
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| * ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-062-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-022-24/+24
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* | Merge pull request #1716 from zeldin/ecp5_fixN. Engelhardt2020-03-091-2/+0
|\ \ | | | | | | ecp5: remove unused parameter from \$__ECP5_PDPW16KD
| * | remove unused parametersN. Engelhardt2020-03-061-3/+0
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| * | ecp5: Add missing parameter to \$__ECP5_PDPW16KDMarcus Comstedt2020-02-221-0/+1
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* | synth_ecp5: use +/abc9_model.vEddie Hung2020-02-271-1/+1
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* | ecp5: remove small LUT entriesEddie Hung2020-02-271-24/+6
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* | ecp5: deprecate abc9_{arrival,required} and *.{lut,box}Eddie Hung2020-02-277-86/+120
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* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-0/+1
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* Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-031-0/+1
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* xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-271-77/+55
| | | | Now done in read_aiger
* Merge remote-tracking branch 'origin/master' into eddie/abc9_mfsEddie Hung2020-01-074-35/+31
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| * Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-064-4/+4
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| * \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-021-2/+2
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| * | | Missing characterEddie Hung2019-12-311-1/+1
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| * | | Cleanup ecp5 boxesEddie Hung2019-12-314-35/+31
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* | | | Re-enable &mfs for synth_{ecp5,xilinx}Eddie Hung2020-01-061-2/+2
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* | | Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-024-4/+4
|\ \ \ | |_|/ |/| | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| * | Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-014-4/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 12:56:47 +0000