iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	ice40: move over to specify blocks for -abc9	Eddie Hung	2020-02-27	1	-6/+0
\|
*	Makefile: don't assume python is called `python3`	Sean Cross	2019-10-19	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
*	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-7/+7
\|
*	Panic over. Model was elsewhere. Re-arrange for consistency	Eddie Hung	2019-10-04	1	-0/+1
\|
*	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-08-20	1	-1/+0
\|\
\| *	Revert "Merge pull request #1280 from ↵	Eddie Hung	2019-08-12	1	-1/+0
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
\| *	Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"	David Shah	2019-08-10	1	-0/+1
\| \|
\| *	Remove ice40_unlut	Eddie Hung	2019-08-07	1	-1/+0
\| \|
* \|	Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing	Eddie Hung	2019-08-08	1	-0/+1
\|/
*	Also update Makefile.inc	Eddie Hung	2019-04-18	1	-7/+6
\|
*	Update Makefile.inc too	Eddie Hung	2019-04-17	1	-4/+6
\|
*	Add "-device" argument to synth_ice40	Eddie Hung	2019-04-17	1	-2/+4
\|
*	Also update Makefile.inc	Eddie Hung	2019-04-17	1	-3/+3
\|
*	Add ice40 box files	Eddie Hung	2019-04-16	1	-0/+3
\|
*	ice40: Add ice40_braminit pass to allow initialization of BRAM from file	Sylvain Munaut	2019-03-08	1	-0/+1
\| \| \| \| \| \| \| \|	This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
*	Extract ice40_unlut pass from ice40_opt.	whitequark	2018-12-05	1	-0/+1
\| \| \| \| \| \| \| \|	Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert them back to logic immediately. This is not desirable if the goal is to operate on $lut cells. If this is desirable, the same result as `ice40_opt -unlut` can be achieved by running simplemap and opt after ice40_unlut.
*	Added synth_ice40 support for latches via logic loops	Clifford Wolf	2016-05-06	1	-0/+1
\|
*	Added ice40_ffinit pass	Clifford Wolf	2015-11-26	1	-0/+1
\|
*	Switched to Python 3	Clifford Wolf	2015-08-22	1	-1/+1
\|
*	Another bugfix for ice40 and xilinx brams_init make rules	Clifford Wolf	2015-08-16	1	-1/+1
\|
*	Fixed Makefile rules for generated share files	Clifford Wolf	2015-08-16	1	-1/+6
\|
*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12	1	-4/+1
\| \| \| \|	This is based on work done by Larry Doolittle
*	Verific build fixes	Clifford Wolf	2015-05-17	1	-2/+2
\|
*	Added iCE40 const folding support for SB_CARRY	Clifford Wolf	2015-04-27	1	-0/+1
\|
*	Initialization support for all iCE40 bram modes	Clifford Wolf	2015-04-26	1	-0/+18
\|
*	Added ice40 bram support	Clifford Wolf	2015-04-24	1	-0/+2
\|
*	Added ice40 SB_CARRY support	Clifford Wolf	2015-04-18	1	-0/+1
\|
*	Added mapping of synchronous set/reset to iCE40 flow	Clifford Wolf	2015-04-17	1	-0/+1
\|
*	Added very first version of "synth_ice40"	Clifford Wolf	2015-03-05	1	-0/+6