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* opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-2/+2
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* synth_ice40: add -relut option, to run ice40_unlut and opt_lut.whitequark2018-12-051-1/+13
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* Extract ice40_unlut pass from ice40_opt.whitequark2018-12-053-13/+109
| | | | | | | | Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert them back to logic immediately. This is not desirable if the goal is to operate on $lut cells. If this is desirable, the same result as `ice40_opt -unlut` can be achieved by running simplemap and opt after ice40_unlut.
* ice40: Add option to only use CE if it'd be use by more than X FFsSylvain Munaut2018-11-271-0/+14
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Add iCE40 SB_SPRAM256KA simulation modelClifford Wolf2018-09-101-9/+30
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-204-10/+10
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LCDavid Shah2018-07-131-2/+6
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add "synth_ice40 -json"Clifford Wolf2018-06-131-9/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix ice40_opt for cases where a port is connected to a signal with width != 1Clifford Wolf2018-06-111-9/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Avoid mixing module port declaration styles in ice40 cells_sim.vOlof Kindgren2018-05-171-43/+23
| | | | | | The current code requires workarounds for several simulators For modelsim, the file must be compiled with -mixedansiports and xsim needs --relax.
* Improving vpr output support.Tim 'mithro' Ansell2018-04-182-4/+4
| | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`.
* synth_ice40: Rework the vpr blif output slightly.Tim 'mithro' Ansell2018-04-181-4/+8
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* Add "synth_ice40 -nodffe"Clifford Wolf2018-04-161-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Squelch trailing whitespace, including meta-whitespaceLarry Doolittle2018-03-111-3/+3
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* Fix port names in SB_IO_ODGraham Edgecombe2017-12-101-18/+18
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* Remove trailing comma from SB_IO_OD port listGraham Edgecombe2017-12-101-1/+1
| | | | This isn't compatible with Icarus Verilog.
* Fix spelling in -vpr help for synth_ice40Tim Ansell2017-12-081-1/+1
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* Add remaining UltraPlus cells to ice40 techlibDavid Shah2017-11-281-0/+263
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* Remove unnecessary keep attributesDavid Shah2017-11-181-5/+5
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* Merge branch 'master' into up5kDavid Shah2017-11-172-5/+29
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| * Add "synth_ice40 -vpr"Clifford Wolf2017-11-162-5/+29
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* | Add some UltraPlus cells to ice40 techlibDavid Shah2017-11-161-0/+103
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* Fix synth_ice40 doc regarding -top defaultClifford Wolf2017-09-291-1/+1
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* iCE40 flow is not experimental anymoreClifford Wolf2016-11-011-1/+1
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* Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiationsClifford Wolf2016-07-082-13/+24
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* Improved ice40_ffinit error reportingClifford Wolf2016-06-301-1/+5
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* Added "deminout"Clifford Wolf2016-06-191-0/+1
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* Added synth_ice40 support for latches via logic loopsClifford Wolf2016-05-063-0/+13
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* Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"Clifford Wolf2016-05-061-3/+15
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* Converted synth_greenpak4 to ScriptPassClifford Wolf2016-04-231-3/+2
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* Added "yosys -D" featureClifford Wolf2016-04-214-7/+7
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* Added ScriptPass helper class for script-like passesClifford Wolf2016-03-311-126/+79
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* Renamed opt_share to opt_mergeClifford Wolf2016-03-311-2/+2
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* Renamed opt_const to opt_exprClifford Wolf2016-03-312-6/+6
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* Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-071-1/+7
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* Added dffsr2dffClifford Wolf2016-02-021-0/+2
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* Re-run ice40_opt in "synth_ice40 -abc2"Clifford Wolf2015-12-221-1/+4
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* Improvements in ice40_optClifford Wolf2015-12-221-5/+16
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* Bugfix in ice40_ffinitClifford Wolf2015-12-221-2/+2
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* Improved ice40_ffinitClifford Wolf2015-12-221-1/+22
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* Added "synth_ice40 -abc2"Clifford Wolf2015-12-081-0/+11
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* Merge pull request #108 from cseed/masterClifford Wolf2015-12-071-1/+3
|\ | | | | Added LO to ICESTORM_LC for LUT cascade route.
| * Added LO to ICESTORM_LC for LUT cascade route.Cotton Seed2015-12-061-1/+3
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* | Added ice40_ffinit passClifford Wolf2015-11-263-0/+145
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* | Fixed WE/RE usage in iCE40 BRAM mappingClifford Wolf2015-11-241-8/+8
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* | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handlingClifford Wolf2015-11-061-2/+2
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* | Added read-enable to memory modelClifford Wolf2015-09-252-6/+8
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* | Fixed ice40 handling of negclk RAM40Clifford Wolf2015-09-102-12/+12
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* | Switched to Python 3Clifford Wolf2015-08-222-5/+2
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* Another bugfix for ice40 and xilinx brams_init make rulesClifford Wolf2015-08-162-4/+4
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