| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-30 | 3 | -3/+3 |
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| | * | Rename boxes too | Eddie Hung | 2019-08-29 | 3 | -3/+3 |
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| | * | Do not overwrite LUT param | Eddie Hung | 2019-08-28 | 1 | -1/+0 |
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| * | | Comment out SB_MAC16 arrival time for now, need to handle all its modes | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| * | | Add arrival for SB_MAC16.O | Eddie Hung | 2019-08-28 | 1 | -0/+1 |
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| * | | Add arrival times for U | Eddie Hung | 2019-08-28 | 1 | -0/+26 |
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| * | | LX -> LP | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| * | | Round not floor | Eddie Hung | 2019-08-28 | 1 | -21/+21 |
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| * | | Add LP timings | Eddie Hung | 2019-08-28 | 1 | -0/+26 |
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| * | | LX -> LP | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| * | | Do not overwrite LUT param | Eddie Hung | 2019-08-28 | 1 | -1/+0 |
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| * | | Merge remote-tracking branch 'origin/eddie/fix_carry_wrapper' into xaig_arrival | Eddie Hung | 2019-08-28 | 2 | -1/+48 |
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| | * | Trailing comma | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| | * | Adapt to $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-28 | 1 | -3/+5 |
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| | * | Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with" | Eddie Hung | 2019-08-28 | 1 | -0/+45 |
| | | | | | | | | | This reverts commit 2aedee1f0e0f6a6214241f51f5c12d4b67c3ef6f. | ||||
| * | | Add arrival times for HX devices | Eddie Hung | 2019-08-28 | 1 | -21/+114 |
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| * | | Specify ice40 family to cells_sim.v using define | Eddie Hung | 2019-08-28 | 1 | -1/+8 |
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| * | Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with | Eddie Hung | 2019-08-28 | 1 | -45/+0 |
| | | | | | CARRY_WRAPPER in the same way since I0 and I3 could be used | ||||
| * | Update box size and timings | Eddie Hung | 2019-08-28 | 3 | -12/+12 |
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| * | Update to new $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-28 | 1 | -11/+8 |
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| * | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 1 | -2/+4 |
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| * | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 1 | -2/+8 |
| |\ | | | | | Refactor abc9 to use port attributes, not module attributes | ||||
| | * | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -2/+2 |
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| | * | Update abc_* attr in ecp5 and ice40 | Eddie Hung | 2019-08-16 | 1 | -2/+8 |
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| * | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-12 | 1 | -1/+1 |
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| * | | Revert "Merge pull request #1280 from ↵ | Eddie Hung | 2019-08-12 | 6 | -150/+32 |
| |/ | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. | ||||
| * | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 6 | -32/+150 |
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| * | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 3 | -5/+5 |
| |\ | | | | | Cleanup a few barnacles across codebase | ||||
| | * | substr() -> compare() | Eddie Hung | 2019-08-07 | 1 | -3/+3 |
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| | * | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -1/+1 |
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| | * | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -1/+1 |
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| * | | Allow whitebox modules to be overwritten | Eddie Hung | 2019-08-07 | 1 | -2/+0 |
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| * | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER | Eddie Hung | 2019-08-07 | 3 | -10/+17 |
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| * | | Add test | Eddie Hung | 2019-08-07 | 1 | -1/+10 |
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| * | | Remove ice40_unlut | Eddie Hung | 2019-08-07 | 2 | -107/+0 |
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| * | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER | Eddie Hung | 2019-08-07 | 3 | -39/+14 |
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| * | ice40: Fix test_dsp_model.sh | David Shah | 2019-07-19 | 1 | -1/+1 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ice40/cells_sim.v: Fix sign of J and K partial products | David Shah | 2019-07-19 | 1 | -5/+7 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode | David Shah | 2019-07-19 | 1 | -2/+2 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Add tests for all combinations of A and B signedness for comb mul | Eddie Hung | 2019-07-19 | 2 | -1/+229 |
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| * | Don't copy ref if exists already | Eddie Hung | 2019-07-19 | 1 | -1/+3 |
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| * | Merge pull request #1184 from whitequark/synth-better-labels | Clifford Wolf | 2019-07-18 | 1 | -2/+2 |
| |\ | | | | | synth_{ice40,ecp5}: more sensible pass label naming | ||||
| | * | synth_{ice40,ecp5}: more sensible pass label naming. | whitequark | 2019-07-16 | 1 | -2/+2 |
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| * | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map | Sylvain Munaut | 2019-07-16 | 2 | -4/+4 |
| | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
| * | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix | Eddie Hung | 2019-07-16 | 8 | -29/+120 |
| |\ \ | |/ |/| | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box | ||||
| | * | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark | Eddie Hung | 2019-07-15 | 7 | -8/+8 |
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| | * | ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT | Eddie Hung | 2019-07-13 | 1 | -9/+7 |
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| | * | Use Const::from_string() not its constructor... | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
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| | * | Off by one | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
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| | * | Fix spacing | Eddie Hung | 2019-07-12 | 1 | -1/+1 |
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index : iCE40/yosys | |
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