| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | Update box size and timings | Eddie Hung | 2019-08-28 | 3 | -12/+12 | |
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| | * | Update to new $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-28 | 1 | -11/+8 | |
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| | * | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 1 | -2/+4 | |
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| | * | Merge pull request #1304 from YosysHQ/eddie/abc9_refactor | Eddie Hung | 2019-08-20 | 1 | -2/+8 | |
| | |\ | | | | | | | Refactor abc9 to use port attributes, not module attributes | |||||
| | | * | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro | Eddie Hung | 2019-08-19 | 1 | -2/+2 | |
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| | | * | Update abc_* attr in ecp5 and ice40 | Eddie Hung | 2019-08-16 | 1 | -2/+8 | |
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| | * | | Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-08-12 | 1 | -1/+1 | |
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| | * | | Revert "Merge pull request #1280 from ↵ | Eddie Hung | 2019-08-12 | 6 | -150/+32 | |
| | |/ | | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. | |||||
| * | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-12 | 3 | -5/+5 | |
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| | * | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" | David Shah | 2019-08-10 | 6 | -32/+150 | |
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| | * | Merge pull request #1258 from YosysHQ/eddie/cleanup | Clifford Wolf | 2019-08-10 | 3 | -5/+5 | |
| | |\ | | | | | | | Cleanup a few barnacles across codebase | |||||
| | | * | substr() -> compare() | Eddie Hung | 2019-08-07 | 1 | -3/+3 | |
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| | | * | RTLIL::S{0,1} -> State::S{0,1} | Eddie Hung | 2019-08-07 | 1 | -1/+1 | |
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| | | * | stoi -> atoi | Eddie Hung | 2019-08-07 | 1 | -1/+1 | |
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| | * | | Allow whitebox modules to be overwritten | Eddie Hung | 2019-08-07 | 1 | -2/+0 | |
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| | * | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER | Eddie Hung | 2019-08-07 | 3 | -10/+17 | |
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| | * | | Add test | Eddie Hung | 2019-08-07 | 1 | -1/+10 | |
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| | * | | Remove ice40_unlut | Eddie Hung | 2019-08-07 | 2 | -107/+0 | |
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| | * | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER | Eddie Hung | 2019-08-07 | 3 | -39/+14 | |
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| * | | Add wreduce to synth_ice40 -dsp as well | Eddie Hung | 2019-08-09 | 1 | -0/+1 | |
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| * | | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing | Eddie Hung | 2019-08-08 | 3 | -1/+36 | |
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| * | | Run "opt_expr -fine" instead of "wreduce" due to #1213 | Eddie Hung | 2019-08-07 | 1 | -2/+1 | |
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| * | | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH | Eddie Hung | 2019-08-01 | 1 | -1/+1 | |
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| * | | Remove debug | Eddie Hung | 2019-07-22 | 1 | -1/+0 | |
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| * | | Rename according to vendor doc TN1295 | Eddie Hung | 2019-07-22 | 1 | -0/+1 | |
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| * | | opt and wreduce necessary for -dsp | Eddie Hung | 2019-07-22 | 1 | -2/+4 | |
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| * | | Indirection via $__soft_mul | Eddie Hung | 2019-07-19 | 1 | -0/+1 | |
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| * | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this threshold | Eddie Hung | 2019-07-19 | 1 | -1/+1 | |
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| * | | Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 3 | -7/+239 | |
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| | * | ice40: Fix test_dsp_model.sh | David Shah | 2019-07-19 | 1 | -1/+1 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | ice40/cells_sim.v: Fix sign of J and K partial products | David Shah | 2019-07-19 | 1 | -5/+7 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode | David Shah | 2019-07-19 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | Add tests for all combinations of A and B signedness for comb mul | Eddie Hung | 2019-07-19 | 2 | -1/+229 | |
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| | * | Don't copy ref if exists already | Eddie Hung | 2019-07-19 | 1 | -1/+3 | |
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| * | | Fix SB_MAC sim model -- do not sign extend internal products? | Eddie Hung | 2019-07-18 | 1 | -2/+2 | |
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| * | | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 9 | -35/+126 | |
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| | * | Merge pull request #1184 from whitequark/synth-better-labels | Clifford Wolf | 2019-07-18 | 1 | -2/+2 | |
| | |\ | | | | | | | synth_{ice40,ecp5}: more sensible pass label naming | |||||
| | | * | synth_{ice40,ecp5}: more sensible pass label naming. | whitequark | 2019-07-16 | 1 | -2/+2 | |
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| | * | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map | Sylvain Munaut | 2019-07-16 | 2 | -4/+4 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | |||||
| | * | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix | Eddie Hung | 2019-07-16 | 8 | -29/+120 | |
| | |\ \ | | |/ | |/| | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box | |||||
| | | * | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark | Eddie Hung | 2019-07-15 | 7 | -8/+8 | |
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| | | * | ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT | Eddie Hung | 2019-07-13 | 1 | -9/+7 | |
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| | | * | Use Const::from_string() not its constructor... | Eddie Hung | 2019-07-12 | 1 | -1/+1 | |
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| | | * | Off by one | Eddie Hung | 2019-07-12 | 1 | -1/+1 | |
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| | | * | Fix spacing | Eddie Hung | 2019-07-12 | 1 | -1/+1 | |
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| | | * | Remove double push | Eddie Hung | 2019-07-12 | 1 | -1/+0 | |
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| | | * | Map to and from this box if -abc9 | Eddie Hung | 2019-07-12 | 1 | -2/+3 | |
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| | | * | ice40_opt to handle this box and opt back to SB_LUT4 | Eddie Hung | 2019-07-12 | 1 | -0/+48 | |
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| | | * | Add new box to cells_sim.v | Eddie Hung | 2019-07-12 | 1 | -2/+25 | |
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| | | * | _ABC macro will map and unmap to this new box | Eddie Hung | 2019-07-12 | 2 | -0/+34 | |
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index : iCE40/yosys | |
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