| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add "synth_intel --noiopads" | Clifford Wolf | 2018-04-30 | 1 | -2/+11 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal ↵ | c60k28 | 2018-03-31 | 1 | -4/+23 |
| | | | | | value for the POWER_UP parameter. Fixed and tested Cyclone V device | ||||
| * | Add "dffinit -highlow" and fix synth_intel | Clifford Wolf | 2018-01-09 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Initial Cyclone 10 support | dh73 | 2017-11-08 | 1 | -1/+5 |
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| * | Clean whitespace and permissions in techlibs/intel | Larry Doolittle | 2017-10-05 | 1 | -3/+3 |
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| * | Rename "write_verilog -nobasenradix" to "write_verilog -decimal" | Clifford Wolf | 2017-10-03 | 1 | -4/+1 |
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| * | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵ | dh73 | 2017-10-01 | 1 | -0/+241 |
| M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now | |||||
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index : iCE40/yosys | |
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