| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | synth_intel: Warn about untested Quartus backend | Dan Ravensloft | 2019-07-07 | 1 | -0/+3 |
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| * | Fix formatting for synth_intel.cc | Ben Widawsky | 2019-05-09 | 1 | -222/+211 |
| | | | | | | | This is realized through the recently added .clang-format file. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| * | Fixing issues in CycloneV cell sim | Diego | 2019-04-11 | 1 | -3/+9 |
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| * | Reduce amount of trailing whitespace in code base | Larry Doolittle | 2019-02-28 | 2 | -7/+7 |
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| * | Unify usage of noflatten among architectures | Miodrag Milanovic | 2019-01-04 | 1 | -2/+2 |
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| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -1/+1 |
| | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually. | ||||
| * | Changes in GoWin synth commands and ALU primitive support | Diego H | 2018-12-03 | 1 | -8/+8 |
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| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -6/+6 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Add "synth_intel --noiopads" | Clifford Wolf | 2018-04-30 | 1 | -2/+11 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal ↵ | c60k28 | 2018-03-31 | 7 | -60/+178 |
| | | | | | value for the POWER_UP parameter. Fixed and tested Cyclone V device | ||||
| * | Add "dffinit -highlow" and fix synth_intel | Clifford Wolf | 2018-01-09 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Initial Cyclone 10 support | dh73 | 2017-11-08 | 5 | -1/+308 |
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| * | Clean whitespace and permissions in techlibs/intel | Larry Doolittle | 2017-10-05 | 21 | -190/+190 |
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| * | Rename "write_verilog -nobasenradix" to "write_verilog -decimal" | Clifford Wolf | 2017-10-03 | 1 | -4/+1 |
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| * | Tested and working altsyncarm without init files | dh73 | 2017-10-01 | 2 | -57/+59 |
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| * | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵ | dh73 | 2017-10-01 | 21 | -0/+2721 |
| M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now | |||||
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index : iCE40/yosys | |
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