| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add "dffinit -highlow" and fix synth_intel | Clifford Wolf | 2018-01-09 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Initial Cyclone 10 support | dh73 | 2017-11-08 | 5 | -1/+308 |
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| * | Clean whitespace and permissions in techlibs/intel | Larry Doolittle | 2017-10-05 | 21 | -190/+190 |
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| * | Rename "write_verilog -nobasenradix" to "write_verilog -decimal" | Clifford Wolf | 2017-10-03 | 1 | -4/+1 |
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| * | Tested and working altsyncarm without init files | dh73 | 2017-10-01 | 2 | -57/+59 |
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| * | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵ | dh73 | 2017-10-01 | 21 | -0/+2721 |
| M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now | |||||
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index : iCE40/yosys | |
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