iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	intel_alm: Add global buffer insertion	gatecat	2021-05-15	1	-2/+4
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-27	1	-0/+34
\| \| \| \|	This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
*	intel_alm: add additional ABC9 timings	Dan Ravensloft	2020-07-23	1	-4/+9
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*	Revert "intel_alm: direct M10K instantiation"	Lofty	2020-07-13	1	-34/+0
\| \| \| \|	This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-05	1	-0/+34
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*	intel_alm: ABC9 sequential optimisations	Dan Ravensloft	2020-07-04	1	-0/+10
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*	intel_alm: direct LUTRAM cell instantiation	Dan Ravensloft	2020-05-07	1	-0/+60
	By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.