iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-05	5	-34/+117
\|
*	intel_alm: DSP inference	Dan Ravensloft	2020-07-05	4	-0/+135
\|
*	synth_intel_alm: Use dfflegalize.	Marcelina Kościelnicka	2020-07-04	1	-117/+6
\|
*	Improve MISTRAL_FF specify rules	Dan Ravensloft	2020-07-04	1	-5/+4
\| \| \| \|	Co-authored-by: Eddie Hung <eddie@fpgeh.com>
*	intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF	Eddie Hung	2020-07-04	2	-47/+2
\|
*	intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY	Eddie Hung	2020-07-04	3	-3/+3
\|
*	intel_alm: ABC9 sequential optimisations	Dan Ravensloft	2020-07-04	5	-10/+126
\|
*	Add force_downto and force_upto wire attributes.	Marcelina Kościelnicka	2020-05-19	2	-0/+8
\| \| \| \|	Fixes #2058.
*	intel_alm: direct LUTRAM cell instantiation	Dan Ravensloft	2020-05-07	6	-50/+141
\| \| \| \| \| \| \| \| \| \|	By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
*	intel_alm: cleanup duplication	Dan Ravensloft	2020-04-24	1	-0/+63
\|
*	intel_alm: Documentation improvements	Dan Ravensloft	2020-04-21	3	-14/+127
\|
*	synth_intel_alm: VQM support	Dan Ravensloft	2020-04-15	1	-6/+2
\|
*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	13	-0/+1082
	By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).