iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	intel_alm: M10K write-enable is negative-true	Lofty	2022-03-09	1	-2/+1
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*	intel_alm: preliminary Arria V support	Lofty	2021-11-25	1	-3/+8
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*	Fixing old e-mail addresses and deadnames	Claire Xenia Wolf	2021-06-08	1	-1/+1
\| \| \| \| \| \| \| \|	s/((Claire\|Xen\|Xenia\|Clifford)\s+)+(Wolf\|Xen)\s+<(claire\|clifford)@(symbioticeda.com\|clifford.at\|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina\|Nak\|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com\|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave\|david)@(symbioticeda.com\|yosyshq.com\|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag\|micko)@(symbioticeda.com\|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
*	intel_alm: Add global buffer insertion	gatecat	2021-05-15	1	-1/+11
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	intel_alm: Add IO buffer insertion	gatecat	2021-05-15	1	-2/+12
\| \| \| \|	Signed-off-by: gatecat <gatecat@ds0.me>
*	Blackbox all whiteboxes after synthesis	gatecat	2021-03-17	1	-0/+1
\| \| \| \| \| \| \|	This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
*	intel_alm: better map wide but shallow multiplies	Dan Ravensloft	2020-08-28	1	-2/+6
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*	intel_alm: Add multiply signedness to cells	Dan Ravensloft	2020-08-26	1	-4/+4
\| \| \| \| \| \|	Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
*	intel: move Cyclone V support to intel_alm	Dan Ravensloft	2020-08-20	1	-1/+1
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*	Replace opt_rmdff with opt_dff.	Marcelina Kościelnicka	2020-08-07	1	-3/+2
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*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-27	1	-1/+2
\| \| \| \|	This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
*	intel_alm: increase abc9 -W	Dan Ravensloft	2020-07-26	1	-1/+1
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*	Revert "intel_alm: direct M10K instantiation"	Lofty	2020-07-13	1	-2/+1
\| \| \| \|	This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
*	intel_alm: direct M10K instantiation	Dan Ravensloft	2020-07-05	1	-1/+2
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*	intel_alm: DSP inference	Dan Ravensloft	2020-07-05	1	-9/+49
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*	synth_intel_alm: Use dfflegalize.	Marcelina Kościelnicka	2020-07-04	1	-4/+3
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*	intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY	Eddie Hung	2020-07-04	1	-1/+1
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*	intel_alm: ABC9 sequential optimisations	Dan Ravensloft	2020-07-04	1	-9/+20
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*	Use C++11 final/override keywords.	whitequark	2020-06-18	1	-4/+4
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*	intel_alm: fix DFFE matching	Dan Ravensloft	2020-06-11	1	-1/+1
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*	synth_*: no need to explicitly read +/abc9_model.v	Eddie Hung	2020-05-14	1	-1/+0
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*	intel_alm: direct LUTRAM cell instantiation	Dan Ravensloft	2020-05-07	1	-1/+1
\| \| \| \| \| \| \| \| \| \|	By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
*	intel_alm: cleanup duplication	Dan Ravensloft	2020-04-24	1	-2/+1
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*	intel_alm: work around a Quartus ICE	Dan Ravensloft	2020-04-23	1	-0/+10
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*	synth_intel_alm: VQM support	Dan Ravensloft	2020-04-15	1	-0/+1
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*	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	1	-0/+240
	By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).