aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/intel_alm/synth_intel_alm.cc
Commit message (Collapse)AuthorAgeFilesLines
* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-5/+8
| | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* intel_alm: M10K write-enable is negative-trueLofty2022-03-091-2/+1
|
* intel_alm: preliminary Arria V supportLofty2021-11-251-3/+8
|
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* intel_alm: Add global buffer insertiongatecat2021-05-151-1/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add IO buffer insertiongatecat2021-05-151-2/+12
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: better map wide but shallow multipliesDan Ravensloft2020-08-281-2/+6
|
* intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-261-4/+4
| | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
* intel: move Cyclone V support to intel_almDan Ravensloft2020-08-201-1/+1
|
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+2
|
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-271-1/+2
| | | | This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-1/+1
|
* Revert "intel_alm: direct M10K instantiation"Lofty2020-07-131-2/+1
| | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-051-1/+2
|
* intel_alm: DSP inferenceDan Ravensloft2020-07-051-9/+49
|
* synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-041-4/+3
|
* intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLYEddie Hung2020-07-041-1/+1
|
* intel_alm: ABC9 sequential optimisationsDan Ravensloft2020-07-041-9/+20
|
* Use C++11 final/override keywords.whitequark2020-06-181-4/+4
|
* intel_alm: fix DFFE matchingDan Ravensloft2020-06-111-1/+1
|
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+0
|
* intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-071-1/+1
| | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* intel_alm: cleanup duplicationDan Ravensloft2020-04-241-2/+1
|
* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+10
|
* synth_intel_alm: VQM supportDan Ravensloft2020-04-151-0/+1
|
* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-151-0/+240
By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-02 22:59:03 +0000