| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | intel_alm: cleanup duplication | Dan Ravensloft | 2020-04-24 | 5 | -113/+64 |
| | | |||||
| * | intel_alm: work around a Quartus ICE | Dan Ravensloft | 2020-04-23 | 1 | -0/+10 |
| | | |||||
| * | intel_alm: Documentation improvements | Dan Ravensloft | 2020-04-21 | 3 | -14/+127 |
| | | |||||
| * | synth_intel_alm: VQM support | Dan Ravensloft | 2020-04-15 | 2 | -6/+3 |
| | | |||||
| * | synth_intel_alm: alternative synthesis for Intel FPGAs | Dan Ravensloft | 2020-04-15 | 17 | -0/+1453 |
| By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6). | |||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |