aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx
Commit message (Collapse)AuthorAgeFilesLines
* Add Xilinx dist RAM as comb boxesEddie Hung2019-06-242-0/+16
|
* Add comment to xc7 boxEddie Hung2019-06-221-0/+3
|
* Carry in/out box ordering now move to end, not swap with endEddie Hung2019-06-221-12/+12
|
* Remove DFF and RAMD box info for nowEddie Hung2019-06-212-36/+0
|
* Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abcEddie Hung2019-06-201-0/+1
|
* Really permute Xilinx LUT mappings as default LUT6.I5:A6Eddie Hung2019-06-181-16/+16
|
* Revert "Fix (do not) permute LUT inputs, but permute mux selects"Eddie Hung2019-06-181-33/+31
| | | | This reverts commit da3d2eedd2b6391621e81b3eaaa28a571e058f9d.
* Fix (do not) permute LUT inputs, but permute mux selectsEddie Hung2019-06-181-31/+33
|
* Fix copy-pasta issueEddie Hung2019-06-171-9/+8
|
* Permute INIT for +/xilinx/lut_map.vEddie Hung2019-06-171-32/+58
|
* Simplify commentEddie Hung2019-06-171-1/+1
|
* Update LUT7/8 delays to take account for [ABC]OUTMUX delayEddie Hung2019-06-171-5/+5
|
* Try -W 300Eddie Hung2019-06-171-1/+2
|
* Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> OEddie Hung2019-06-151-2/+2
|
* As per @daveshah1 remove async DFF timing from xilinxEddie Hung2019-06-141-2/+2
|
* Add XC7_WIRE_DELAY macro to synth_xilinx.ccEddie Hung2019-06-141-1/+3
|
* Update delays based on SymbiFlow/prjxray-dbEddie Hung2019-06-141-12/+13
|
* Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}Eddie Hung2019-06-144-3/+3
|
* Remove WIP ABC9 flop supportEddie Hung2019-06-142-18/+18
|
* Make doc consistentEddie Hung2019-06-141-1/+1
|
* Fix name clashEddie Hung2019-06-131-4/+8
|
* Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-06-121-0/+8
|
* Reduce diff with masterEddie Hung2019-06-121-1/+1
|
* Fix spacingEddie Hung2019-06-121-6/+6
|
* Remove wide mux inferenceEddie Hung2019-06-124-194/+3
|
* Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
|
* Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
| | | | This reverts commit 2dffa4685b830313204f5d04314a14ed6ecac8ec.
* Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-111-1/+1
|
* Disable dist RAM boxes due to comb loopEddie Hung2019-06-111-2/+2
|
* Remove #ifndef ABCEddie Hung2019-06-111-4/+0
|
* Revert "Revert "Move ff_map back after ABC for shregmap""Eddie Hung2019-06-101-5/+5
| | | | This reverts commit e473e7456545d702c011ee7872956f94a8522865.
* Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"Eddie Hung2019-06-101-2/+2
| | | | This reverts commit 94a5f4e60985fc1e3fea75eec85638fa29874bea.
* Comment out muxpack (currently broken)Eddie Hung2019-06-071-2/+2
|
* $__XILINX_MUX_ -> $__XILINX_SHIFTXEddie Hung2019-06-062-11/+11
|
* Fix muxcover and its techmappingEddie Hung2019-06-062-3/+3
|
* Run muxpack and muxcover in synth_xilinxEddie Hung2019-06-062-1/+18
|
* Remove abc_flop attributes for nowEddie Hung2019-06-061-56/+10
|
* Update abc attributes on FD*E_1Eddie Hung2019-06-051-6/+26
|
* CleanupEddie Hung2019-06-052-17/+0
|
* Call shregmap -tech xilinx_staticEddie Hung2019-06-051-1/+1
|
* Revert "Move ff_map back after ABC for shregmap"Eddie Hung2019-06-051-4/+4
| | | | This reverts commit 9b9bd4e19f3da363eb3c90ef27ace282716d2e06.
* Rename shregmap -tech xilinx -> xilinx_dynamicEddie Hung2019-06-041-2/+2
|
* Add space between -D and _ABCEddie Hung2019-06-041-2/+2
|
* Add (* abc_flop_q *) to brams_bb.vEddie Hung2019-06-041-8/+8
|
* Fix name clashEddie Hung2019-06-041-11/+11
|
* Add mux_map.v for wide muxEddie Hung2019-06-044-30/+82
|
* Move ff_map back after ABC for shregmapEddie Hung2019-06-031-4/+4
|
* Respect -nocarryEddie Hung2019-06-031-1/+3
|
* Fix pmux2shiftx logicEddie Hung2019-06-031-1/+1
|
* Merge mistakeEddie Hung2019-06-031-14/+6
|