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* Remove $_MUX4_ techmap ruleEddie Hung2019-06-211-11/+0
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* Fix wreduce call (!!!), tweak muxcover costsEddie Hung2019-06-211-5/+6
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* Constrain wreduce only if wide muxEddie Hung2019-06-211-1/+4
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* Simplify and comment out mux_map.vEddie Hung2019-06-211-6/+11
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* synth_xilinx to now wreduce except $mux, remove extra peepoptEddie Hung2019-06-211-8/+1
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* mux_map to no longer copy last value into 1'bxEddie Hung2019-06-211-19/+2
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* Fix spacingEddie Hung2019-06-211-3/+3
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* Fix spacing again, A_forward -> A_backwardEddie Hung2019-06-211-38/+40
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* Restore wreduce to synth_xilinx, after muxcoverEddie Hung2019-06-211-0/+1
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* Revert B_SIGNED optimisation, since only works for Y_WIDTH==1Eddie Hung2019-06-211-4/+3
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* Fix spacingEddie Hung2019-06-211-15/+15
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* synth_xilinx to use _ABC macro, and perform muxpack againEddie Hung2019-06-211-5/+5
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* Add $__XILINX_MUXF78 to preserve entire boxEddie Hung2019-06-213-7/+28
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* Fix alignmentEddie Hung2019-06-211-1/+1
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* Add FIXME about need for -mux4Eddie Hung2019-06-211-0/+2
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* Since muxcover uses MUX4s, blast them back to gates hereEddie Hung2019-06-211-0/+7
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* Expand synth -coarse without wreduce, move muxcoverEddie Hung2019-06-211-12/+24
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* Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abcEddie Hung2019-06-201-0/+1
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* mux_map to drop sign bit, and eliminate 'bx-esEddie Hung2019-06-201-13/+47
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* Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-181-29/+27
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| * Really permute Xilinx LUT mappings as default LUT6.I5:A6Eddie Hung2019-06-181-16/+16
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| * Revert "Fix (do not) permute LUT inputs, but permute mux selects"Eddie Hung2019-06-181-33/+31
| | | | | | | | This reverts commit da3d2eedd2b6391621e81b3eaaa28a571e058f9d.
* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-181-31/+33
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| * Fix (do not) permute LUT inputs, but permute mux selectsEddie Hung2019-06-181-31/+33
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* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-9/+8
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| * Fix copy-pasta issueEddie Hung2019-06-171-9/+8
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* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-172-33/+59
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| * Permute INIT for +/xilinx/lut_map.vEddie Hung2019-06-171-32/+58
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| * Simplify commentEddie Hung2019-06-171-1/+1
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* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-5/+5
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| * Update LUT7/8 delays to take account for [ABC]OUTMUX delayEddie Hung2019-06-171-5/+5
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| * Try -W 300Eddie Hung2019-06-171-1/+2
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* | Try -W 300Eddie Hung2019-06-161-1/+2
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* | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-151-2/+2
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| * Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> OEddie Hung2019-06-151-2/+2
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* | Revert "Remove wide mux inference"Eddie Hung2019-06-144-3/+194
|/ | | | This reverts commit 738fdfe8f55e18ac7f315cd68c117eae370004ca.
* As per @daveshah1 remove async DFF timing from xilinxEddie Hung2019-06-141-2/+2
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* Add XC7_WIRE_DELAY macro to synth_xilinx.ccEddie Hung2019-06-141-1/+3
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* Update delays based on SymbiFlow/prjxray-dbEddie Hung2019-06-141-12/+13
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* Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}Eddie Hung2019-06-144-3/+3
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* Remove WIP ABC9 flop supportEddie Hung2019-06-142-18/+18
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* Make doc consistentEddie Hung2019-06-141-1/+1
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* Fix name clashEddie Hung2019-06-131-4/+8
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* Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-06-121-0/+8
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* Reduce diff with masterEddie Hung2019-06-121-1/+1
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* Fix spacingEddie Hung2019-06-121-6/+6
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* Remove wide mux inferenceEddie Hung2019-06-124-194/+3
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* Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
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* Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-1/+1
| | | | This reverts commit 2dffa4685b830313204f5d04314a14ed6ecac8ec.
* Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-111-1/+1
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