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xilinx
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Author
Age
Files
Lines
*
Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-22
2
-48
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+15
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Add comment to xc7 box
Eddie Hung
2019-06-22
1
-0
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+3
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Carry in/out box ordering now move to end, not swap with end
Eddie Hung
2019-06-22
1
-12
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+12
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Remove DFF and RAMD box info for now
Eddie Hung
2019-06-21
2
-36
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+0
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Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
Eddie Hung
2019-06-20
1
-0
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+1
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Remove $_MUX4_ techmap rule
Eddie Hung
2019-06-21
1
-11
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+0
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Fix wreduce call (!!!), tweak muxcover costs
Eddie Hung
2019-06-21
1
-5
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+6
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Constrain wreduce only if wide mux
Eddie Hung
2019-06-21
1
-1
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+4
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Simplify and comment out mux_map.v
Eddie Hung
2019-06-21
1
-6
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+11
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synth_xilinx to now wreduce except $mux, remove extra peepopt
Eddie Hung
2019-06-21
1
-8
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+1
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mux_map to no longer copy last value into 1'bx
Eddie Hung
2019-06-21
1
-19
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+2
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Fix spacing
Eddie Hung
2019-06-21
1
-3
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+3
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Fix spacing again, A_forward -> A_backward
Eddie Hung
2019-06-21
1
-38
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+40
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Restore wreduce to synth_xilinx, after muxcover
Eddie Hung
2019-06-21
1
-0
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+1
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Revert B_SIGNED optimisation, since only works for Y_WIDTH==1
Eddie Hung
2019-06-21
1
-4
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+3
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Fix spacing
Eddie Hung
2019-06-21
1
-15
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+15
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synth_xilinx to use _ABC macro, and perform muxpack again
Eddie Hung
2019-06-21
1
-5
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+5
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Add $__XILINX_MUXF78 to preserve entire box
Eddie Hung
2019-06-21
3
-7
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+28
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Fix alignment
Eddie Hung
2019-06-21
1
-1
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+1
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Add FIXME about need for -mux4
Eddie Hung
2019-06-21
1
-0
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+2
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Since muxcover uses MUX4s, blast them back to gates here
Eddie Hung
2019-06-21
1
-0
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+7
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Expand synth -coarse without wreduce, move muxcover
Eddie Hung
2019-06-21
1
-12
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+24
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Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc
Eddie Hung
2019-06-20
1
-0
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+1
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mux_map to drop sign bit, and eliminate 'bx-es
Eddie Hung
2019-06-20
1
-13
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+47
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-18
1
-29
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+27
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Really permute Xilinx LUT mappings as default LUT6.I5:A6
Eddie Hung
2019-06-18
1
-16
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+16
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Revert "Fix (do not) permute LUT inputs, but permute mux selects"
Eddie Hung
2019-06-18
1
-33
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+31
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This reverts commit da3d2eedd2b6391621e81b3eaaa28a571e058f9d.
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-18
1
-31
/
+33
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\
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*
Fix (do not) permute LUT inputs, but permute mux selects
Eddie Hung
2019-06-18
1
-31
/
+33
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-17
1
-9
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+8
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\
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Fix copy-pasta issue
Eddie Hung
2019-06-17
1
-9
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+8
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-17
2
-33
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+59
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\
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Permute INIT for +/xilinx/lut_map.v
Eddie Hung
2019-06-17
1
-32
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+58
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Simplify comment
Eddie Hung
2019-06-17
1
-1
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+1
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-17
1
-5
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+5
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\
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Update LUT7/8 delays to take account for [ABC]OUTMUX delay
Eddie Hung
2019-06-17
1
-5
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+5
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Try -W 300
Eddie Hung
2019-06-17
1
-1
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+2
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Try -W 300
Eddie Hung
2019-06-16
1
-1
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+2
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-15
1
-2
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+2
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\
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Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O
Eddie Hung
2019-06-15
1
-2
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+2
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Revert "Remove wide mux inference"
Eddie Hung
2019-06-14
4
-3
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+194
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This reverts commit 738fdfe8f55e18ac7f315cd68c117eae370004ca.
*
As per @daveshah1 remove async DFF timing from xilinx
Eddie Hung
2019-06-14
1
-2
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+2
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Add XC7_WIRE_DELAY macro to synth_xilinx.cc
Eddie Hung
2019-06-14
1
-1
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+3
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Update delays based on SymbiFlow/prjxray-db
Eddie Hung
2019-06-14
1
-12
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+13
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Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
Eddie Hung
2019-06-14
4
-3
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+3
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Remove WIP ABC9 flop support
Eddie Hung
2019-06-14
2
-18
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+18
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Make doc consistent
Eddie Hung
2019-06-14
1
-1
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+1
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Fix name clash
Eddie Hung
2019-06-13
1
-4
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+8
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Move neg-pol to pos-pol mapping from ff_map to cells_map.v
Eddie Hung
2019-06-12
1
-0
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+8
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Reduce diff with master
Eddie Hung
2019-06-12
1
-1
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+1
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