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* Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
|\ | | | | Changes required for VPR place and route in synth_xilinx
| * Revert BRAM WRITE_MODE changes.Keith Rothman2019-03-041-12/+12
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Revert FF models to include IS_x_INVERTED parameters.Keith Rothman2019-03-011-6/+34
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Use singular for disabling of DRAM or BRAM inference.Keith Rothman2019-03-011-13/+13
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Modify arguments to match existing style.Keith Rothman2019-03-011-6/+6
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Changes required for VPR place and route synth_xilinx.Keith Rothman2019-03-0111-221/+587
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Use "write_edif -pvector bra" for Xilinx EDIF filesClifford Wolf2019-03-051-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Add support for Xilinx PS7 blockEddie Hung2018-11-102-0/+624
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* xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.Tim 'mithro' Ansell2018-10-081-3/+2
| | | | | Then if targeting vpr map all the Xilinx specific LUTs back into generic Yosys LUTs.
* Add inout ports to cells_xtra.vClifford Wolf2018-10-042-2/+14
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* xilinx: Adding missing inout IO port to IOBUFTim Ansell2018-10-031-0/+1
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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* Improving vpr output support.Tim 'mithro' Ansell2018-04-182-3/+36
| | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`.
* Squelch trailing whitespace, including meta-whitespaceLarry Doolittle2018-03-111-8/+8
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* Add Xilinx RAM64X1D and RAM128X1D simulation modelsClifford Wolf2018-03-074-23/+30
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* Add techlibs/xilinx/lut2lut.vClifford Wolf2017-07-102-0/+66
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* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
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* Added black box modules for all the 7-series design elements (as listed in ↵Clifford Wolf2016-03-194-0/+3441
| | | | ug953)
* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-131-0/+2
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* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-011-2/+2
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* Bugfix in Xilinx LUT mappingClifford Wolf2015-10-301-1/+1
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* Added examples/ top-level directoryClifford Wolf2015-10-137-77/+0
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* Added read-enable to memory modelClifford Wolf2015-09-253-19/+23
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* Switched to Python 3Clifford Wolf2015-08-222-5/+2
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* Another bugfix for ice40 and xilinx brams_init make rulesClifford Wolf2015-08-162-5/+5
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* Fixed Makefile rules for generated share filesClifford Wolf2015-08-161-1/+7
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* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-121-6/+2
| | | | This is based on work done by Larry Doolittle
* Fixed trailing whitespacesClifford Wolf2015-07-023-6/+6
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* Added output args to synth_ice40Clifford Wolf2015-05-261-2/+2
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* Verific build fixesClifford Wolf2015-05-171-2/+2
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* Improved xilinx "bram1" testClifford Wolf2015-04-091-1/+2
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* Added memory_bram "make_outreg" featureClifford Wolf2015-04-091-0/+2
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* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-093-13/+67
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* Towards DRAM support in Xilinx flowClifford Wolf2015-04-095-0/+78
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* Added support for initialized xilinx bramsClifford Wolf2015-04-0610-91/+314
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* Added Xilinx test case for initialized bramsClifford Wolf2015-04-064-0/+80
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* Added Xilinx bram black-box modulesClifford Wolf2015-04-063-0/+322
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* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-041-5/+6
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* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-151-0/+2
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* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-151-0/+10
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* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-041-6/+6
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* no support for 6-series xilinx devicesClifford Wolf2015-02-011-1/+1
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* Removed old XST-based xilinx examplesClifford Wolf2015-02-0111-208/+0
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* Added Xilinx example for Basys3 boardClifford Wolf2015-02-019-1/+84
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* Added missing ports and parameters to xilinx bramsClifford Wolf2015-02-011-4/+18
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* Fixed xilinx FDSE sim modelClifford Wolf2015-01-241-2/+2
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* Various cleanups in xilinx techlibClifford Wolf2015-01-187-9/+110
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* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-183-468/+55
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* Added synth_xilinx -retime -flattenClifford Wolf2015-01-171-2/+28
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