| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Resolve TODO with pin assignments for SRL* | Eddie Hung | 2019-09-04 | 1 | -4/+2 |
| | | |||||
| * | Add comments | Eddie Hung | 2019-09-02 | 1 | -1/+9 |
| | | |||||
| * | Remove trailing space | Eddie Hung | 2019-08-30 | 1 | -2/+2 |
| | | |||||
| * | Merge branch 'eddie/xilinx_srl' into xaig_arrival | Eddie Hung | 2019-08-28 | 1 | -15/+22 |
| |\ | |||||
| | * | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-28 | 7 | -194/+623 |
| | |\ | |||||
| | * \ | Merge branch 'master' into eddie/xilinx_srl | Eddie Hung | 2019-08-26 | 1 | -0/+8 |
| | |\ \ | |||||
| | * | | | xilinx_srl now copes with word-level flops $dff{,e} | Eddie Hung | 2019-08-23 | 1 | -8/+3 |
| | | | | | |||||
| | * | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 1 | -8/+16 |
| | |\ \ \ | |||||
| | * | | | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 1 | -4/+3 |
| | | | | | | |||||
| | * | | | | abc9 to perform new 'map_ffs' before 'map_luts' | Eddie Hung | 2019-08-21 | 1 | -3/+18 |
| | | | | | | |||||
| | * | | | | Add init support | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
| | | | | | | |||||
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-28 | 7 | -195/+653 |
| |\ \ \ \ \ | |||||
| | * | | | | | Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor | Eddie Hung | 2019-08-28 | 1 | -3/+8 |
| | | |_|_|/ | |/| | | | |||||
| | * | | | | xilinx: Add SRLC16E primitive. | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+21 |
| | | | | | | | | | | | | | | | | | | | | | Fixes #1331. | ||||
| | * | | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 1 | -0/+8 |
| | |\ \ \ \ | | | |_|/ | | |/| | | |||||
| | | * | | | Add undocumented feature | Eddie Hung | 2019-08-23 | 1 | -0/+8 |
| | | | |/ | | |/| | |||||
| | * | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
| | |\| | | |||||
| | * | | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 1 | -11/+22 |
| | |\ \ \ | |||||
| | * \ \ \ | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 5 | -30/+39 |
| | |\ \ \ \ | | | |_|/ | | |/| | | |||||
| | * | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 6 | -283/+537 |
| | | | | | | |||||
| | * | | | | minor review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -1/+1 |
| | | | | | | |||||
| | * | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 1 | -18/+27 |
| | | | | | | |||||
| | * | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 6 | -71/+220 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | ||||
| * | | | | | Put attributes above port | Eddie Hung | 2019-08-23 | 2 | -27/+62 |
| | | | | | | |||||
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrival | Eddie Hung | 2019-08-23 | 1 | -5/+10 |
| |\ \ \ \ \ | | |_|_|/ | |/| | | | |||||
| | * | | | | Forgot one | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
| | | |_|/ | |/| | | |||||
| | * | | | Put abc_* attributes above port | Eddie Hung | 2019-08-23 | 1 | -7/+14 |
| | | |/ | |/| | |||||
| * | | | Use semicolon | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
| | | | | |||||
| * | | | techmap before read | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
| | | | | |||||
| * | | | Add abc_arrival to SRL* | Eddie Hung | 2019-08-21 | 1 | -3/+5 |
| | | | | |||||
| * | | | Oops | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
| | | | | |||||
| * | | | xilinx to use abc_map.v with -max_iter 1 | Eddie Hung | 2019-08-20 | 6 | -171/+26 |
| | | | | |||||
| * | | | Add reference to FD* timing | Eddie Hung | 2019-08-20 | 1 | -0/+2 |
| | | | | |||||
| * | | | Remove sequential extension | Eddie Hung | 2019-08-20 | 6 | -359/+17 |
| | | | | |||||
| * | | | Remove SRL* delays from cells_sim.v | Eddie Hung | 2019-08-20 | 1 | -5/+3 |
| | | | | |||||
| * | | | LUTMUX -> LUTMUX6 | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
| | | | | |||||
| * | | | Cleanup techmap in map_luts | Eddie Hung | 2019-08-20 | 1 | -3/+5 |
| | | | | |||||
| * | | | Move `techmap abc_map.v` into map_luts | Eddie Hung | 2019-08-20 | 1 | -1/+2 |
| | | | | |||||
| * | | | Remove delays from abc_map.v | Eddie Hung | 2019-08-20 | 1 | -5/+2 |
| | | | | |||||
| * | | | Typo | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
| | | | | |||||
| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-08-20 | 4 | -16/+19 |
| |\| | | |||||
| | * | | Merge pull request #1209 from YosysHQ/eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 4 | -16/+19 |
| | |\ \ | | | | | | | | | [WIP] synth xilinx renaming, as per #1184 | ||||
| | | * | | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx | Eddie Hung | 2019-08-20 | 3 | -6/+6 |
| | | |\| | |||||
| | | * | | Update Makefile too | Eddie Hung | 2019-07-18 | 1 | -2/+2 |
| | | | | | |||||
| | | * | | Work in progress for renaming labels/options in synth_xilinx | Eddie Hung | 2019-07-18 | 3 | -14/+17 |
| | | | | | |||||
| * | | | | Wrap SRL{16,32} too | Eddie Hung | 2019-08-20 | 3 | -7/+98 |
| | | | | | |||||
| * | | | | Wrap LUTRAMs in order to capture comb/seq behaviour | Eddie Hung | 2019-08-20 | 5 | -36/+200 |
| | | | | | |||||
| * | | | | Add LUTRAM delays | Eddie Hung | 2019-08-20 | 1 | -3/+6 |
| | | | | | |||||
| * | | | | Remove mapping rules | Eddie Hung | 2019-08-20 | 1 | -33/+0 |
| | | | | | |||||
| * | | | | Remove -icells | Eddie Hung | 2019-08-20 | 1 | -2/+2 |
| | | | | | |||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |