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* Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-0639-656/+1189
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| * Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2020-01-0212-756/+722
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| | * synth_xilinx -dff to work with abc tooEddie Hung2020-01-021-6/+14
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| | * Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-0214-66/+86
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| | * | Update commentsEddie Hung2020-01-021-11/+6
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| | * | abc9 -keepff -> -dff; refactor dff operationsEddie Hung2020-01-022-58/+58
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| | * | Clamp -46ps for FDPE* tooEddie Hung2020-01-011-2/+2
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| | * | Restore abc9 -keepffEddie Hung2020-01-012-86/+6
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| | * | Re-arrange FD orderEddie Hung2019-12-313-182/+182
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| | * | Missing characterEddie Hung2019-12-311-1/+1
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| | * | Cleanup xilinx boxesEddie Hung2019-12-312-391/+425
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| | * | Cleanup ice40 boxesEddie Hung2019-12-313-30/+43
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| | * | Cleanup ecp5 boxesEddie Hung2019-12-314-35/+31
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| | * | Update abc9_xc7.box commentsEddie Hung2019-12-311-18/+18
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| | * | FDCE ports to be alphabeticalEddie Hung2019-12-311-3/+3
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| | * | Fix attributes on $__ABC9_ASYNC[01] whiteboxEddie Hung2019-12-311-2/+2
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| | * | Fix incorrect $__ABC9_ASYNC[01] boxEddie Hung2019-12-311-2/+2
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| * | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-0227-91/+118
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| | * \ \ Merge pull request #1604 from whitequark/unify-ram-namingwhitequark2020-01-0218-40/+67
| | |\ \ \ | | | |_|/ | | |/| | Harmonize BRAM/LUTRAM descriptions across all of Yosys
| | | * | Harmonize BRAM/LUTRAM descriptions across all of Yosys.whitequark2020-01-0118-40/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
| | * | | Merge pull request #1601 from YosysHQ/eddie/synth_retimeEddie Hung2020-01-0212-37/+37
| | |\ \ \ | | | | | | | | | | | | "abc -dff" to no longer retime by default
| | | * | | Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-3011-12/+12
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| | | * | | Disable synth_gowin -abc9 as it offers no advantages yetEddie Hung2019-12-301-12/+12
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| | | * | | Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-3011-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
| | * | | | ifdef __ICARUS__ -> ifndef YOSYSEddie Hung2020-01-011-6/+6
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| | * | | | Fix anlogic async flop mappingEddie Hung2020-01-011-8/+8
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| * | | | Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2019-12-306-121/+673
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| | * | Do not offset FD* box timings due to -46ps TsuEddie Hung2019-12-301-12/+21
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| | * | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-3010-32/+377
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| | * | | Tidy up abc9_map.vEddie Hung2019-12-301-103/+103
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| | * | | Add "synth_xilinx -dff" option, cleanup abc9Eddie Hung2019-12-302-2/+98
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| | * | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-24/+10
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| | * \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-204-172/+240
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| | * | | | | Add RAM{32,64}M to abc9_map.vEddie Hung2019-12-191-0/+78
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| | * | | | | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-195-36/+55
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| | * | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1914-81/+995
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| | * \ \ \ \ \ Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-1213-30/+32
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| | * | | | | | | abc9_map.v: fix Xilinx LUTRAMEddie Hung2019-12-121-6/+6
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| | * | | | | | | Fix commentEddie Hung2019-12-091-1/+1
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| | * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-067-745/+1138
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| | * | | | | | | | Remove creation of $abc9_control_wireEddie Hung2019-12-061-16/+6
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| | * | | | | | | | abc9 to use mergeability class to differentiate sync/asyncEddie Hung2019-12-061-12/+15
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| | * | | | | | | | Remove clkpartEddie Hung2019-12-051-4/+0
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| | * | | | | | | | Revert "Special abc9_clock wire to contain only clock signal"Eddie Hung2019-12-051-10/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d.
| | * | | | | | | | Missing wire declarationEddie Hung2019-12-041-0/+1
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| | * | | | | | | | abc9_map.v to transform INIT=1 to INIT=0Eddie Hung2019-12-041-118/+201
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| | * | | | | | | | Oh deary meEddie Hung2019-12-041-4/+4
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| | * | | | | | | | output reg Q -> output Q to suppress warningEddie Hung2019-12-041-8/+8
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| | * | | | | | | | abc9_map.v to do `zinit' and make INIT = 1'b0Eddie Hung2019-12-041-70/+112
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| | * | | | | | | | Add abc9_init wire, attach to abc9_flop cellEddie Hung2019-12-031-2/+12
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