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| * | intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-181-28/+10
| | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | The help and code default to MAX10 for the family, however the couple of if ladders defaulted to cycloneive. Fix this inconsistency and the next patch will clean it up. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
| | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* | | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
|/ / | | | | | | Also fix a typo in the help message.
* | Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
|\ \ | | | | | | synth_{ice40,ecp5}: more sensible pass label naming
| * | synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
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| * | synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
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* | | Merge pull request #1204 from smunaut/fix_1187David Shah2019-07-172-4/+4
|\ \ \ | | | | | | | | ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
| * | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-162-4/+4
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* / | gen_lut to return correctly sized LUT maskEddie Hung2019-07-161-1/+1
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* | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-168-29/+120
|\ \ | |/ |/| abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
| * $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-157-8/+8
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| * ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUTEddie Hung2019-07-131-9/+7
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| * Use Const::from_string() not its constructor...Eddie Hung2019-07-121-1/+1
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| * Off by oneEddie Hung2019-07-121-1/+1
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| * Fix spacingEddie Hung2019-07-121-1/+1
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| * Remove double pushEddie Hung2019-07-121-1/+0
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| * Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
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| * ice40_opt to handle this box and opt back to SB_LUT4Eddie Hung2019-07-121-0/+48
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| * Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
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| * _ABC macro will map and unmap to this new boxEddie Hung2019-07-122-0/+34
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| * Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 boxEddie Hung2019-07-123-25/+13
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* | Merge pull request #1183 from whitequark/ice40-always-relutClifford Wolf2019-07-121-11/+5
|\ \ | |/ |/| synth_ice40: switch -relut to be always on
| * synth_ice40: switch -relut to be always on.whitequark2019-07-111-10/+4
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| * synth_ice40: fix help text typo. NFC.whitequark2019-07-111-1/+1
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* | Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
|\ \ | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support.
| * | synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
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* / xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵Marcin Kościelnicki2019-07-112-6/+6
|/ | | | ISE/Vivado.
* Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-103-6/+15
|\ | | | | Error out if -abc9 and -retime specified
| * Error out if -abc9 and -retime specifiedEddie Hung2019-07-103-6/+15
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* | Merge pull request #1148 from YosysHQ/xc7muxEddie Hung2019-07-106-49/+414
|\ \ | |/ |/| synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
| * Add some spacingEddie Hung2019-07-101-9/+9
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| * Add some ASCII art explaining mux decompositionEddie Hung2019-07-101-0/+21
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| * Call muxpack and pmux2shiftx before cmp2lutEddie Hung2019-07-091-9/+12
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| * Restore opt_clean back to original placeEddie Hung2019-07-091-2/+1
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| * Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6Eddie Hung2019-07-091-0/+2
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| * Extend using A[1] to preserve don't careEddie Hung2019-07-091-1/+9
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| * Extend during mux decomposition with 1'bxEddie Hung2019-07-091-24/+3
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| * Fix typo and commentsEddie Hung2019-07-091-4/+4
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| * Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-07-092-19/+28
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| * | synth_xilinx to call commands of synth -coarse directlyEddie Hung2019-07-091-3/+20
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| * | Revert "synth_xilinx to call "synth -run coarse" with "-keepdc""Eddie Hung2019-07-091-2/+2
| | | | | | | | | | | | This reverts commit 7f964859ec99500e471853f5914b6e5b7c35a031.
| * | Fix spacingEddie Hung2019-07-091-1/+1
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| * | Fix spacingEddie Hung2019-07-091-1/+1
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| * | Decompose mux inputs in delay-orientated (rather than area) fashionEddie Hung2019-07-081-18/+30
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| * | Do not call opt -mux_undef (part of -full) before muxcoverEddie Hung2019-07-081-1/+5
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| * | Add one more commentEddie Hung2019-07-081-0/+3
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| * | Less thinkingEddie Hung2019-07-081-3/+3
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| * | RewordEddie Hung2019-07-081-2/+2
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