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| | * | | | | | | | | | | | | | | | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
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| | * | | | | | | | | | | | | | | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
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| | * | | | | | | | | | | | | | | | Working for unsignedEddie Hung2019-07-181-52/+28
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| | * | | | | | | | | | | | | | | | CleanupEddie Hung2019-07-181-70/+58
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| | * | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-181-31/+41
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| | | * | | | | | | | | | | | | | | | mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | | | | | | | | | | Make all operands signedEddie Hung2019-07-171-1/+1
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| | * | | | | | | | | | | | | | | | | Update commentEddie Hung2019-07-171-5/+3
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| | * | | | | | | | | | | | | | | | Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
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| | * | | | | | | | | | | | | | | | A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
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| | * | | | | | | | | | | | | | | | Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
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| | * | | | | | | | | | | | | | | | SignednessEddie Hung2019-07-162-8/+8
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| | * | | | | | | | | | | | | | | | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
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| | * | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-164-27/+35
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| | | * | | | | | | | | | | | | | | | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * | | | | | | | | | | | | | | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵David Shah2019-07-162-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me>
| | | * | | | | | | | | | | | | | | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * | | | | | | | | | | | | | | | mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | | | | | | | | | | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
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| | * | | | | | | | | | | | | | | | | Do not swap if equalsEddie Hung2019-07-151-1/+1
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| | * | | | | | | | | | | | | | | | | Oops forgot these filesEddie Hung2019-07-152-0/+5
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| | * | | | | | | | | | | | | | | | | OUT port to Y in generic DSPEddie Hung2019-07-152-3/+3
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| | * | | | | | | | | | | | | | | | | Move DSP mapping back out to dsp_map.vEddie Hung2019-07-152-41/+40
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| | * | | | | | | | | | | | | | | | Only swap if B_WIDTH > A_WIDTHEddie Hung2019-07-151-1/+1
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| | * | | | | | | | | | | | | | | | Tidy upEddie Hung2019-07-151-39/+26
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| | * | | | | | | | | | | | | | | | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_simEddie Hung2019-07-152-82/+131
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| | * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1512-25/+609
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| | * | | | | | | | | | | | | | | | | Move dsp_map.v into cells_map.v; cleanup synth_xilinx a littleEddie Hung2019-07-104-45/+42
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| | * | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-105-102/+193
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| | * | | | | | | | | | | | | | | | | | xc7: Map combinational DSP48E1sDavid Shah2019-07-084-7/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | | | | | | | | | | | mul2dsp: Fix typoDavid Shah2019-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | | | | | | | | | | | Add mul2dsp multiplier splitting rule and ECP5 mappingDavid Shah2019-07-085-2/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | | | | | | FDCE_1 does not have IS_CLR_INVERTEDEddie Hung2019-09-291-1/+1
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* | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-291-1/+1
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| * | | | | | | | | | | | | | | | | | | Fix box nameEddie Hung2019-09-271-1/+1
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* | | | | | | | | | | | | | | | | | | | Big rework; flop info now mostly in cells_sim.vEddie Hung2019-09-286-295/+314
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* | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-09-2757-1594/+22196
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| * | | | | | | | | | | | | | | | | | | Missing an '&'Eddie Hung2019-09-261-1/+1
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| * | | | | | | | | | | | | | | | | | Use extractinv for synth_xilinx -iseMarcin Kościelnicki2019-09-198-90/+502
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| * | | | | | | | | | | | | | | | | Merge pull request #1379 from mmicko/sim_modelsEddie Hung2019-09-182-7/+162
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added simulation models for Efinix and Anlogic
| | * | | | | | | | | | | | | | | | | make note that it is for latch modeMiodrag Milanovic2019-09-181-0/+1
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| | * | | | | | | | | | | | | | | | | better lut handlingMiodrag Milanovic2019-09-181-4/+14
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| | * | | | | | | | | | | | | | | | | better handling of lut and begin/end addMiodrag Milanovic2019-09-181-4/+10
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| | * | | | | | | | | | | | | | | | | Added simulation models for Efinix and AnlogicMiodrag Milanovic2019-09-152-3/+141
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| * / | | | | | | | | | | | | | | | xilinx: Make blackbox library family-dependent.Marcin Kościelnicki2019-09-157-1024/+19252
| |/ / / / / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1246.
| * | | | | | | | | | | | | | / / synth_xilinx: Support init values on Spartan 6 flip-flops properly.Marcin Kościelnicki2019-09-075-53/+219
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| * | | | | | | | | | | | | | | Resolve TODO with pin assignments for SRL*Eddie Hung2019-09-041-4/+2
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| * | | | | | | | | | | | | | | Add commentsEddie Hung2019-09-021-1/+9
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| * | | | | | | | | | | | | | | Rename boxEddie Hung2019-09-021-1/+1
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| * | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-09-022-7/+8
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