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| | * | | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-157-8/+8
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| | * | | ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUTEddie Hung2019-07-131-9/+7
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| | * | | Use Const::from_string() not its constructor...Eddie Hung2019-07-121-1/+1
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| | * | | Off by oneEddie Hung2019-07-121-1/+1
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| | * | | Fix spacingEddie Hung2019-07-121-1/+1
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| | * | | Remove double pushEddie Hung2019-07-121-1/+0
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| | * | | Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
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| | * | | ice40_opt to handle this box and opt back to SB_LUT4Eddie Hung2019-07-121-0/+48
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| | * | | Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
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| | * | | _ABC macro will map and unmap to this new boxEddie Hung2019-07-122-0/+34
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| | * | | Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 boxEddie Hung2019-07-123-25/+13
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| * | | | Merge pull request #1183 from whitequark/ice40-always-relutClifford Wolf2019-07-121-11/+5
| |\ \ \ \ | | |/ / / | |/| | | synth_ice40: switch -relut to be always on
| | * | | synth_ice40: switch -relut to be always on.whitequark2019-07-111-10/+4
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| | * | | synth_ice40: fix help text typo. NFC.whitequark2019-07-111-1/+1
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| * | | Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
| |\ \ \ | | | | | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support.
| | * | | synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
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| * / / xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵Marcin Kościelnicki2019-07-112-6/+6
| |/ / | | | | | | | | | ISE/Vivado.
* | | Add Tsu offset to boxes, and commentsEddie Hung2019-07-111-6/+11
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* | | ABC doesn't like negative delays in flop boxes...Eddie Hung2019-07-111-6/+6
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* | | Fix FDCE_1 boxEddie Hung2019-07-111-1/+1
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* | | Revert "$pastQ should be first input"Eddie Hung2019-07-111-13/+13
| | | | | | | | | | | | This reverts commit 8f9d529929f43e6ba98f06159ae9533984c6264f.
* | | Propagate INIT attrEddie Hung2019-07-111-5/+5
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* | | $pastQ should be first inputEddie Hung2019-07-111-13/+13
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* | | Fix typoEddie Hung2019-07-111-1/+1
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* | | Simplify to $__ABC_ASYNC boxEddie Hung2019-07-112-19/+8
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* | | $__ABC_FD_ASYNC_MUX.Q -> YEddie Hung2019-07-111-1/+1
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* | | Restore from masterEddie Hung2019-07-101-0/+1
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* | | Another typoEddie Hung2019-07-101-1/+1
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* | | Fix clk_pol for FD*_1Eddie Hung2019-07-101-3/+3
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* | | Another typoEddie Hung2019-07-101-1/+1
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* | | Another typoEddie Hung2019-07-101-1/+1
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* | | Use \$currQEddie Hung2019-07-101-4/+9
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* | | Preserve all parameters, plus some extra ones for clk/en polarityEddie Hung2019-07-101-10/+66
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* | | Change how to specify flops to ABC againEddie Hung2019-07-101-13/+37
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* | | Remove params from FD*_1 variantsEddie Hung2019-07-101-12/+3
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* | | Fix typo, and have !{PRE,CLR} behave as CEEddie Hung2019-07-101-14/+14
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* | | Move ABC FF stuff to abc_ff.v; add support for other FD* typesEddie Hung2019-07-104-27/+135
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* | | Uncomment IS_C_INVERTED parameterEddie Hung2019-07-101-1/+1
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* | | synth_xilinx's map_cells stage to techmap ff_map.vEddie Hung2019-07-101-0/+2
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* | | Fix box numberingEddie Hung2019-07-102-5/+5
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-07-109-77/+457
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| * | Merge pull request #1180 from YosysHQ/eddie/no_abc9_retimeEddie Hung2019-07-103-6/+15
| |\ \ | | | | | | | | Error out if -abc9 and -retime specified
| | * | Error out if -abc9 and -retime specifiedEddie Hung2019-07-103-6/+15
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| * | | Merge pull request #1148 from YosysHQ/xc7muxEddie Hung2019-07-106-49/+414
| |\ \ \ | | |/ / | |/| | synth_xilinx to infer wide multiplexers using new '-widemux <min>' option
| | * | Add some spacingEddie Hung2019-07-101-9/+9
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| | * | Add some ASCII art explaining mux decompositionEddie Hung2019-07-101-0/+21
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| | * | Call muxpack and pmux2shiftx before cmp2lutEddie Hung2019-07-091-9/+12
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| | * | Restore opt_clean back to original placeEddie Hung2019-07-091-2/+1
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| | * | Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6Eddie Hung2019-07-091-0/+2
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| | * | Extend using A[1] to preserve don't careEddie Hung2019-07-091-1/+9
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