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* Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-1814-51/+146
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| * Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
| |\ | | | | | | synth_{ice40,ecp5}: more sensible pass label naming
| | * synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
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| | * synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
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| * | Merge pull request #1204 from smunaut/fix_1187David Shah2019-07-172-4/+4
| |\ \ | | | | | | | | ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
| | * | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-162-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | | gen_lut to return correctly sized LUT maskEddie Hung2019-07-161-1/+1
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| * | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-168-29/+120
| |\ \ | | |/ | |/| abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
| | * $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-157-8/+8
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| | * ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUTEddie Hung2019-07-131-9/+7
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| | * Use Const::from_string() not its constructor...Eddie Hung2019-07-121-1/+1
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| | * Off by oneEddie Hung2019-07-121-1/+1
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| | * Fix spacingEddie Hung2019-07-121-1/+1
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| | * Remove double pushEddie Hung2019-07-121-1/+0
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| | * Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
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| | * ice40_opt to handle this box and opt back to SB_LUT4Eddie Hung2019-07-121-0/+48
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| | * Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
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| | * _ABC macro will map and unmap to this new boxEddie Hung2019-07-122-0/+34
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| | * Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 boxEddie Hung2019-07-123-25/+13
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* | | synth_ice40 to decompose into 16x16Eddie Hung2019-07-181-1/+3
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* | | mul2dsp to create cells that can be interchanged with $mulEddie Hung2019-07-181-1/+7
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* | | Make consistentEddie Hung2019-07-181-1/+2
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* | | Fix signed multiplier decompositionEddie Hung2019-07-181-29/+36
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* | | Use single DSP_SIGNEDONLY macroEddie Hung2019-07-181-1/+1
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* | | Working for unsignedEddie Hung2019-07-181-52/+28
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* | | CleanupEddie Hung2019-07-181-70/+58
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* | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-181-31/+41
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| * | | mul2dsp: Lower partial products always have unsigned inputsDavid Shah2019-07-181-31/+41
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Make all operands signedEddie Hung2019-07-171-1/+1
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* | | | Update commentEddie Hung2019-07-171-5/+3
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* | | Fix mul2dsp signednessEddie Hung2019-07-171-42/+38
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* | | A_SIGNED == B_SIGNED so flip bothEddie Hung2019-07-171-21/+12
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* | | Add DSP_{A,B}_SIGNEDONLY macroEddie Hung2019-07-161-11/+40
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* | | SignednessEddie Hung2019-07-162-8/+8
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* | | Revert drop down to 24x16 multipliers for allEddie Hung2019-07-162-4/+4
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* | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-07-164-27/+35
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| * | | xilinx: Add correct signed behaviour to DSP48E1 modelDavid Shah2019-07-161-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | xilinx: Treat DSP48E1 as 24x17 unsigned for now (actual behaviour is 25x18 ↵David Shah2019-07-162-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | signed) Signed-off-by: David Shah <dave@ds0.me>
| * | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTHDavid Shah2019-07-161-18/+22
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | mul2dsp: Fix indentationDavid Shah2019-07-161-7/+7
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Add support for {A,B,P}REG in DSP48E1Eddie Hung2019-07-161-5/+21
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* | | | Do not swap if equalsEddie Hung2019-07-151-1/+1
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* | | | Oops forgot these filesEddie Hung2019-07-152-0/+5
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* | | | OUT port to Y in generic DSPEddie Hung2019-07-152-3/+3
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* | | | Move DSP mapping back out to dsp_map.vEddie Hung2019-07-152-41/+40
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* | | Only swap if B_WIDTH > A_WIDTHEddie Hung2019-07-151-1/+1
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* | | Tidy upEddie Hung2019-07-151-39/+26
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* | | Move DSP48E1 model out of cells_xtra, initial multiply one in cells_simEddie Hung2019-07-152-82/+131
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* | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1512-25/+609
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| * | Merge pull request #1183 from whitequark/ice40-always-relutClifford Wolf2019-07-121-11/+5
| |\ \ | | |/ | |/| synth_ice40: switch -relut to be always on
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