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* Fix spacingEddie Hung2019-04-161-1/+1
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* Make cells.box whiteboxes not blackboxesEddie Hung2019-04-161-2/+2
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* read_verilog cells_box.v before techmapEddie Hung2019-04-161-1/+1
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* synth_xilinx: before abc read +/xilinx/cells_box.vEddie Hung2019-04-161-0/+1
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* Add +/xilinx/cells_box.v containing models for ABC boxesEddie Hung2019-04-162-0/+11
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* Revert "Add abc_box_id attribute to MUXF7/F8 cells"Eddie Hung2019-04-161-2/+0
| | | | This reverts commit 8fbbd9b129697152c93c35831c1d50982702a3ec.
* Add abc_box_id attribute to MUXF7/F8 cellsEddie Hung2019-04-151-0/+2
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* Merge branch 'xaig' into xc7muxEddie Hung2019-04-153-41/+60
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| * Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-121-1/+9
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| * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-124-44/+69
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| | * Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
| | |\ | | | | | | | | Add additional cells sim models for core 7-series primitives.
| | | * Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | | * Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | | * Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
| | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-04-121-3/+9
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| * | | Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
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* | | Fix cells_map.v some moreEddie Hung2019-04-111-7/+7
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* | | More fine tuningEddie Hung2019-04-111-2/+2
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* | | Fix cells_map.vEddie Hung2019-04-111-7/+7
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* | | Fix typoEddie Hung2019-04-111-1/+1
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* | | Juggle opt calls in synth_xilinxEddie Hung2019-04-112-30/+35
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* | | WIP for cells_map.v -- maybe working?Eddie Hung2019-04-101-32/+27
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* | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1Eddie Hung2019-04-101-31/+38
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* | | Fix for when B_SIGNED = 1Eddie Hung2019-04-101-1/+8
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* | | Update doc for synth_xilinxEddie Hung2019-04-101-7/+8
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* | | ff_map.v after abcEddie Hung2019-04-101-5/+5
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* | | Tidy upEddie Hung2019-04-101-1/+1
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* | | Move map_cells to before map_lutsEddie Hung2019-04-101-11/+12
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* | | WIP for $shiftx to wide muxEddie Hung2019-04-101-1/+63
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* | | Update LUT delaysEddie Hung2019-04-101-11/+8
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* | | Add cells.lut to techlibs/xilinx/Eddie Hung2019-04-092-0/+16
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* | | synth_xilinx to call abc with -lut +/xilinx/cells.lutEddie Hung2019-04-091-2/+2
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* | | Add delays to cells.boxEddie Hung2019-04-091-4/+12
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* | | synth_xilinx with abc9 to use -boxEddie Hung2019-04-091-1/+4
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* | | Add techlibs/xilinx/cells.boxEddie Hung2019-04-092-0/+6
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* | | Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-091-1/+9
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* | Merge branch 'master' into xaigEddie Hung2019-04-0832-384/+1646
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| * xilinx: Add keep attribute where appropriateDavid Shah2019-03-222-25/+31
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873Clifford Wolf2019-03-191-2/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Remove ice40/cells_sim.v hack to avoid warning for blocking memory writesClifford Wolf2019-03-121-19/+0
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix typo in ice40_braminit help msgClifford Wolf2019-03-091-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #859 from smunaut/ice40_braminitClifford Wolf2019-03-094-37/+212
| |\ | | | | | | iCE40 BRAM primitives init from file
| | * ice40: Run ice40_braminit pass by defaultSylvain Munaut2019-03-081-0/+1
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| | * ice40: Add ice40_braminit pass to allow initialization of BRAM from fileSylvain Munaut2019-03-083-37/+211
| | | | | | | | | | | | | | | | | | | | | | | | This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will initialize content from a hex file. Same behavior is imlemented in the simulation model and in a new pass for actual synthesis Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | Add link to SF2 / igloo2 macro library guideClifford Wolf2019-03-071-21/+24
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improvements in sf2 cells_sim.vClifford Wolf2019-03-062-30/+251
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add sf2 techmap rules for more FF typesClifford Wolf2019-03-061-25/+39
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Refactor SF2 iobuf insertion, Add clkint insertionClifford Wolf2019-03-063-83/+152
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improvements in SF2 flow and demoClifford Wolf2019-03-052-8/+23
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #842 from litghost/merge_upstreamClifford Wolf2019-03-0510-176/+570
| |\ \ | | | | | | | | Changes required for VPR place and route in synth_xilinx
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