aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Collapse)AuthorAgeFilesLines
...
* | | Merge pull request #1708 from rqou/coolrunner2-buf-fixClaire Wolf2020-02-274-54/+163
|\ \ \ | | | | | | | | coolrunner2: Separate and improve buffer cell insertion pass
| * | | coolrunner2: Separate and improve buffer cell insertion passR. Ou2020-02-164-54/+163
| |/ / | | | | | | | | | | | | | | | | | | The new pass will contain all of the logic for inserting "passthrough" product term and XOR cells as appropriate for the architecture. For example, this commit fixes connecting an input pin directly to another output pin with no logic in between.
* / / xilinx: mark IOBUFDSE3 IOB pin as externalPiotr Binkowski2020-02-272-1/+2
|/ /
* | Remove executable flag from filesMiodrag Milanovic2020-02-155-0/+0
| |
* | abc9: deprecate abc9_ff.init wire for (* abc9_init *) attrEddie Hung2020-02-131-11/+12
| |
* | abc9: cleanupEddie Hung2020-02-101-40/+40
|/
* Remove unnecessary commaEddie Hung2020-02-071-3/+2
|
* techmap: fix shiftx2mux decompositionEddie Hung2020-02-071-8/+6
|
* xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-074-27/+22
| | | | | | | There are multiple other kinds of RAMs supported on these devices, but RAM16X1D is the only dual-port one. Fixes #1549
* xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-073-53/+152
| | | | | | | Adds support for mapping logic, including LUTs, wide LUTs, and carry chains. Fixes #1547
* Merge pull request #1685 from dh73/gowinEddie Hung2020-02-061-1/+1
|\ | | | | Removing cells_sim from GoWin bram techmap
| * Removing cells_sim.v from bram techmap passDiego H2020-02-061-1/+1
| |
* | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-0711-1/+370
| |
* | xilinx: Add support for Spartan 3A DSP block RAMs.Marcin Kościelnicki2020-02-073-1/+39
| | | | | | | | Part of #1550
* | Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_mapEddie Hung2020-02-061-109/+43
|\ \ | |/ |/| Fix/cleanup +/xilinx/arith_map.v
| * Fix $lcu -> MUXCY mapping, credit @mwkmwkmwkEddie Hung2020-02-061-4/+5
| |
| * Fix/cleanup +/xilinx/arith_map.vEddie Hung2020-02-061-111/+44
| |
* | synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-058-5/+9
| |
* | shiftx2mux: fix select out of boundsEddie Hung2020-02-051-1/+2
|/
* Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-0524-359/+1041
|\
| * Merge pull request #1661 from YosysHQ/eddie/abc9_requiredEddie Hung2020-02-057-144/+375
| |\ | | | | | | abc9: add support for required times
| | * Merge branch 'eddie/abc9_refactor' into eddie/abc9_requiredEddie Hung2020-01-275-129/+99
| | |\
| | * \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-151-1/+1
| | |\ \ | | | | | | | | | | | | | | | eddie/abc9_required
| | * | | abc9_ops: -write_box is empty, output a dummy box to prevent ABC errorEddie Hung2020-01-152-2/+0
| | | | |
| | * | | abc9_ops: generate flop box ids, add abc9_required to FD* cellsEddie Hung2020-01-141-12/+45
| | | | |
| | * | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-143-23/+30
| | |\ \ \ | | | | | | | | | | | | | | | | | | eddie/abc9_required
| | * \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-122-3/+2
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| | * | | | | Add abc9_required to DSP48E1.{A,B,C,D,PCIN}Eddie Hung2020-01-101-38/+117
| | | | | | |
| | * | | | | abc9_ops -prep_times: generate flop boxes from abc9_required attrEddie Hung2020-01-101-61/+0
| | | | | | |
| | * | | | | Add abc9_ops -check, -prep_times, -write_box for required timesEddie Hung2020-01-101-0/+5
| | | | | | |
| | * | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-086-1676/+520
| | |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | eddie/abc9_required
| | * \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/abc9_refactor' into ↵Eddie Hung2020-01-0639-656/+1189
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | xaig_arrival_required
| | | * \ \ \ \ \ Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2020-01-0212-756/+722
| | | |\ \ \ \ \ \
| | | * \ \ \ \ \ \ Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-0227-91/+118
| | | |\ \ \ \ \ \ \
| | | * \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactorEddie Hung2019-12-306-121/+673
| | | |\ \ \ \ \ \ \ \
| | * | | | | | | | | | ConsistencyEddie Hung2019-12-271-1/+1
| | | | | | | | | | | |
| | * | | | | | | | | | Update some abc9_arrival times, add abc9_required timesEddie Hung2019-12-273-24/+220
| | | | | | | | | | | |
| * | | | | | | | | | | Add opt_lut_ins pass. (#1673)Marcelina Kościelnicka2020-02-033-0/+3
| | | | | | | | | | | |
| * | | | | | | | | | | xilinx: use RAM32M/RAM64M for memories with two read portsMarcin Kościelnicki2020-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes inefficient LUT RAM usage for memories with one write and two read ports (commonly used as register files).
| * | | | | | | | | | | Merge pull request #1659 from YosysHQ/clifford/experimentalClaire Wolf2020-01-291-1/+1
| |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | Add log_experimental() and experimental() API and "yosys -x"
| | * | | | | | | | | | | Add log_experimental() and experimental() API and "yosys -x"Claire Wolf2020-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
| * | | | | | | | | | | | synth_xilinx: cleanup helpEddie Hung2020-01-281-6/+4
| | | | | | | | | | | | |
| * | | | | | | | | | | | synth_xilinx: fix help when no active_design; fixes #1664Eddie Hung2020-01-281-2/+3
| | | | | | | | | | | | |
| * | | | | | | | | | | | xilinx: Add simulation model for DSP48 (Virtex 4).Marcin Kościelnicki2020-01-296-45/+534
| | | | | | | | | | | | |
| * | | | | | | | | | | | Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_lutsEddie Hung2020-01-284-148/+100
| |\ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unpermute LUT ordering for ice40/ecp5/xilinx
| | * | | | | | | | | | | | Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwardsEddie Hung2020-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like Verilog...
| | * | | | | | | | | | | | Import tests from #1628Eddie Hung2020-01-271-2/+2
| | | | | | | | | | | | | |
| | * | | | | | | | | | | | xilinx/ice40/ecp5: undo permuting LUT masks in lut_mapEddie Hung2020-01-273-146/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now done in read_aiger
| * | | | | | | | | | | | | Fix unresolved conflict from #1573Eddie Hung2020-01-281-1/+1
| | | | | | | | | | | | | |
| * | | | | | | | | | | | | Merge pull request #1573 from YosysHQ/eddie/xilinx_tristateN. Engelhardt2020-01-281-0/+3
| |\ \ \ \ \ \ \ \ \ \ \ \ \ | | |/ / / / / / / / / / / / | |/| | | | | | | | | | | | synth_xilinx: error out if tristate without '-iopad'
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 01:56:41 +0000