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* Add "min bits" and "min wports" to xilinx dram rulesEddie Hung2019-05-231-0/+4
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* Add "wreduce -keepdc", fixes #1016Clifford Wolf2019-05-201-2/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ice40/cells_sim.v: Add support for TRIM input to SB_HFOSCSylvain Munaut2019-05-131-0/+11
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Add "stat -tech xilinx"Clifford Wolf2019-05-111-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix formatting for synth_intel.ccBen Widawsky2019-05-091-222/+211
| | | | | | This is realized through the recently added .clang-format file. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
* Add "synth_xilinx -arch"Clifford Wolf2019-05-071-1/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-036-178/+124
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| * Rename cells_map.v to prevent clash with ff_map.vEddie Hung2019-05-031-6/+8
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| * Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-032-0/+4
| |\ | | | | | | Improve pmgen, Add "peepopt" pass with shift-mul pattern
| | * Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-302-0/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Back to passing all xc7srl tests!Eddie Hung2019-05-011-5/+4
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| * | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fineEddie Hung2019-05-013-170/+104
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| | * \ Merge pull request #966 from YosysHQ/clifford/fix956Clifford Wolf2019-04-301-1/+1
| | |\ \ | | | | | | | | | | Drive dangling wires with init attr with their init value
| | | * | Add handling of init attributes in "opt_expr -undriven"Clifford Wolf2019-04-301-1/+1
| | | |/ | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Refactor synth_xilinx to auto-generate docEddie Hung2019-04-261-153/+95
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| | * | Cleanup ice40Eddie Hung2019-04-261-4/+6
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| * | WIPEddie Hung2019-04-281-36/+22
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| * | Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-04-282-9/+12
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| * | Revert synth_xilinx 'fine' label more to how it used to be...Eddie Hung2019-04-261-21/+40
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| * | Where did this check come from!?!Eddie Hung2019-04-261-1/+0
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* | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Improve $specrule interfaceClifford Wolf2019-04-231-3/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+28
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-70/+70
| | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add $specify2 and $specify3 cells to simlibClifford Wolf2019-04-231-0/+147
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Update help messageEddie Hung2019-04-221-1/+1
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* Move 'shregmap -tech xilinx' into map_cellsEddie Hung2019-04-221-17/+20
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* Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-2212-21/+480
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| * Merge pull request #941 from Wren6991/sim_lib_io_clkeClifford Wolf2019-04-221-10/+19
| |\ | | | | | | ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
| | * ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware ↵Luke Wren2019-04-211-10/+19
| | | | | | | | | | | | experiments
| * | Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-masterClifford Wolf2019-04-2210-10/+458
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| | * | GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flowDiego2019-04-1210-11/+459
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| * | Re-added clean after techmap in synth_xilinxClifford Wolf2019-04-221-0/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #916 from YosysHQ/map_cells_before_map_lutsClifford Wolf2019-04-221-10/+10
| |\ \ | | | | | | | | synth_xilinx to map_cells before map_luts
| * \ \ Merge pull request #911 from mmicko/gowin-nobramClifford Wolf2019-04-221-1/+1
| |\ \ \ | | | | | | | | | | Make nobram false by default for gowin
| | * | | Make nobram false by default for gowinMiodrag Milanovic2019-04-021-1/+1
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* | | | | Tidy up, fix for -nosrlEddie Hung2019-04-212-12/+16
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* | | | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-211-2/+2
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| * | | | Merge branch 'master' into map_cells_before_map_lutsEddie Hung2019-04-216-59/+85
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* | | | | Add commentsEddie Hung2019-04-211-0/+7
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* | | | | Use new pmux2shiftx from #944, remove my old attemptEddie Hung2019-04-211-3/+8
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* | | | | Merge remote-tracking branch 'origin' into xc7srlEddie Hung2019-04-204-44/+69
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| * | | | Revert "synth_* with -retime option now calls abc with -D 1 as well"Eddie Hung2019-04-1811-15/+15
| | | | | | | | | | | | | | | | | | | | This reverts commit 9a6da9a79a22e984ee3eec02caa230b66f10e11a.
| * | | | Merge branch 'master' into eddie/fix_retimeEddie Hung2019-04-184-44/+69
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| | * | | Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
| | |\ \ \ | | | | | | | | | | | | Add additional cells sim models for core 7-series primitives.
| | | * | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | | * | | Fix LUT6_2 definition.Keith Rothman2019-04-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | | * | | Add additional cells sim models for core 7-series primatives.Keith Rothman2019-04-091-0/+57
| | | | |/ | | | |/| | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| | * / | Fixing issues in CycloneV cell simDiego2019-04-111-3/+9
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| * | | synth_* with -retime option now calls abc with -D 1 as wellEddie Hung2019-04-1011-15/+15
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