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* | | Move shregmap until after first techmapEddie Hung2019-03-131-2/+2
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* | | Refactor $__SHREG__ in cells_map.vEddie Hung2019-03-131-32/+24
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* | | Remove SRL16/32 from cells_xtraEddie Hung2019-02-282-18/+2
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* | | Add SRL16 and SRL32 sim modelsEddie Hung2019-02-281-0/+39
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* | | Fix SRL16/32 techmap off-by-oneEddie Hung2019-02-281-18/+24
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* | | synth_xilinx to call shregmap with enable supportEddie Hung2019-02-282-24/+29
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* | | synth_xilinx to use shregmap with -params tooEddie Hung2019-02-282-22/+19
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* | | synth_xilinx to now have shregmap call after dff2dffeEddie Hung2019-02-281-0/+2
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* | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32Eddie Hung2019-02-281-0/+71
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* | Merge pull request #740 from daveshah1/improve_dressClifford Wolf2019-02-222-3/+3
|\ \ | | | | | | Improve ABC netname preservation
| * | ecp5: Use abc -dressDavid Shah2019-02-061-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ice40: Use abc -dress in synth_ice40David Shah2019-02-061-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | | Bugfix in ice40_dspClifford Wolf2019-02-212-20/+33
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add ice40 test_dsp_map test case generatorClifford Wolf2019-02-202-0/+99
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add "synth_ice40 -dsp"Clifford Wolf2019-02-201-3/+27
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Improve iCE40 SB_MAC16 modelClifford Wolf2019-02-205-121/+179
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add first draft of functional SB_MAC16 modelClifford Wolf2019-02-194-53/+467
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
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* Add SF2 IO buffer insertionClifford Wolf2019-01-174-1/+168
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #777 from mmicko/achronix_cell_sim_fixClifford Wolf2019-01-041-1/+1
|\ | | | | Fix cells_sim.v for Achronix FPGA
| * Fix cells_sim.v for Achronix FPGAMiodrag Milanovic2019-01-041-1/+1
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* | Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-044-8/+16
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* Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
|\ | | | | anlogic: implement DRAM initialization
| * anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
| | | | | | | | | | | | | | | | | | | | | | As the TD tool doesn't accept the DRAM cell to contain unknown values in the initial value, the initialzation support of DRAM is previously skipped. Now add the support by add a new pass to determine unknown values in the initial value. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-022-14/+15
|\ \ | | | | | | Initialization of Anlogic DFFs
| * | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As dffinit has already supported for different initialization strings for DFFs and check for re-initialization, initialization of Anlogic DFFs are now ready to go. Support for set the init values of Anlogic DFFs. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | | Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-022-7/+41
|\ \ \ | | | | | | | | synth: add k-LUT mode
| * | | synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
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| * | | synth: add k-LUT mode.whitequark2019-01-021-2/+36
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| * | | synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
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* | | | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-022-1/+106
|\| | | | | | | | | | | cmp2lut: new techmap pass
| * | | cmp2lut: new techmap pass.whitequark2019-01-022-1/+106
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* | | | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-0215-22/+22
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* | | Merge pull request #766 from Icenowy/anlogic-latchesClifford Wolf2018-12-311-0/+12
|\ \ \ | | | | | | | | anlogic: add latch cells
| * | | anlogic: add latch cellsIcenowy Zheng2018-12-251-0/+12
| | |/ | |/| | | | | | | | | | | | | | | | Add latch cells to Anlogic cells replacement library by copying other FPGAs' latch code to it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* / | Fix 7 instances of add_share_file to add_gen_share_fileLarry Doolittle2018-12-291-8/+8
|/ / | | | | | | in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
* | Merge pull request #752 from Icenowy/anlogic-lut-costClifford Wolf2018-12-191-1/+1
|\ \ | | | | | | Anlogic: let LUT5/6 have more cost than LUT4-
| * | Anlogic: let LUT5/6 have more cost than LUT4-Icenowy Zheng2018-12-191-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s. So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost 2x resource of a LUT5. Change the -lut parameter passed to the abc command to pass this cost info to the ABC process. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Merge pull request #753 from Icenowy/anlogic-makefile-fixClifford Wolf2018-12-191-0/+1
|\ \ | | | | | | anlogic: fix Makefile.inc
| * | anlogic: fix Makefile.incIcenowy Zheng2018-12-191-0/+1
| |/ | | | | | | | | | | | | | | | | During the addition of DRAM inferring support, the installation of eagle_bb.v is accidentally removed. Fix this issue. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* / anlogic: fix dbits of Anlogic Eagle DRAM16X4Icenowy Zheng2018-12-181-1/+1
|/ | | | | | | | | The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM bits. Fix the dbits number in the RAM configuration. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* anlogic: add support for Eagle Distributed RAMIcenowy Zheng2018-12-174-1/+43
| | | | | | | | | | | | | The MSLICEs on the Eagle series of FPGA can be configured as Distributed RAM. Enable to synthesis to DRAM. As the Anlogic software suite doesn't support any 'bx to exist in the initializtion data of DRAM, do not enable the initialization support of the inferred DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Revert "Leave only real black box cells"Icenowy Zheng2018-12-171-0/+312
| | | | | | | | | | | This reverts commit 43030db5fff285de85096aaf5578b0548659f6b7. For a synthesis tool, generating EG_LOGIC cells are a good choice, as they can be furtherly optimized when PnR, although sometimes EG_LOGIC is not as blackbox as EG_PHY cells (because the latter is more close to the hardware implementation). Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* Rename "fine:" label to "map:" in "synth_ice40"Clifford Wolf2018-12-161-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-161-0/+2
|\ | | | | equiv_opt: new command, for verifying optimization passes
| * equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-071-0/+2
| | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models.
* | Merge pull request #730 from smunaut/ffssr_dont_touchClifford Wolf2018-12-161-0/+3
|\ \ | | | | | | ice40: Honor the "dont_touch" attribute in FFSSR pass
| * | ice40: Honor the "dont_touch" attribute in FFSSR passSylvain Munaut2018-12-081-0/+3
| |/ | | | | | | | | | | | | This is useful if you want to place FF manually ... can't merge SR in those because it might make the manual placement invalid Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #725 from olofk/ram4k-initClifford Wolf2018-12-161-0/+19
|\ \ | | | | | | Only use non-blocking assignments of SB_RAM40_4K for yosys
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