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* ecp5: Adding synchronous set/reset supportDavid Shah2018-07-142-21/+42
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Add DRAM match ruleDavid Shah2018-07-131-0/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Cells and mappings fixesDavid Shah2018-07-132-5/+5
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fixing arith_mapDavid Shah2018-07-131-4/+5
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Initial arith_map implementationDavid Shah2018-07-133-6/+80
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Adding basic synth_ecp5 based on synth_ice40David Shah2018-07-133-7/+345
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Adding DFF mapsDavid Shah2018-07-132-1/+30
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Adding DRAM mapDavid Shah2018-07-133-1/+76
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7David Shah2018-07-132-0/+473
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LCDavid Shah2018-07-131-2/+6
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add "synth_ice40 -json"Clifford Wolf2018-06-131-9/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix ice40_opt for cases where a port is connected to a signal with width != 1Clifford Wolf2018-06-111-9/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make -nordff the default in "prep"Clifford Wolf2018-05-301-9/+13
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Avoid mixing module port declaration styles in ice40 cells_sim.vOlof Kindgren2018-05-171-43/+23
| | | | | | The current code requires workarounds for several simulators For modelsim, the file must be compiled with -mixedansiports and xsim needs --relax.
* Merge pull request #537 from mithro/yosys-vprClifford Wolf2018-05-044-11/+48
|\ | | | | Improving Yosys when used with VPR
| * Improving vpr output support.Tim 'mithro' Ansell2018-04-184-7/+40
| | | | | | | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`.
| * synth_ice40: Rework the vpr blif output slightly.Tim 'mithro' Ansell2018-04-181-4/+8
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* | Add "synth_intel --noiopads"Clifford Wolf2018-04-301-2/+11
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add "synth_ice40 -nodffe"Clifford Wolf2018-04-161-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal ↵c60k282018-03-3111-178/+233
| | | | value for the POWER_UP parameter. Fixed and tested Cyclone V device
* coolrunner2: Add an ANDTERM/XOR between chained FFsRobert Ou2018-03-311-0/+58
| | | | | | | In some cases (e.g. the low bits of counters) the design might end up with a flip-flop whose input is directly driven by another flip-flop. This isn't possible in the Coolrunner-II architecture, so add a single AND term and XOR in this case.
* coolrunner2: Split multi-bit netsRobert Ou2018-03-311-0/+1
| | | | | The PAR tool doesn't expect any "dangling" nets with no drivers nor sinks. By splitting the nets, clean removes them.
* coolrunner2: Add extraction for TFFsRobert Ou2018-03-313-0/+54
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* Squelch trailing whitespace, including meta-whitespaceLarry Doolittle2018-03-114-16/+16
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* Add Xilinx RAM64X1D and RAM128X1D simulation modelsClifford Wolf2018-03-074-23/+30
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* Add "synth -noshare"Clifford Wolf2018-03-041-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-0/+24
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* coolrunner2: Move LOC attributes onto the IO cellsRobert Ou2018-01-171-0/+2
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* Add "dffinit -highlow" and fix synth_intelClifford Wolf2018-01-091-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix minor typo in "prep" help messageClifford Wolf2017-12-191-1/+1
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* Fix port names in SB_IO_ODGraham Edgecombe2017-12-101-18/+18
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* Remove trailing comma from SB_IO_OD port listGraham Edgecombe2017-12-101-1/+1
| | | | This isn't compatible with Icarus Verilog.
* Fix spelling in -vpr help for synth_ice40Tim Ansell2017-12-081-1/+1
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* Merge pull request #462 from daveshah1/up5kClifford Wolf2017-11-281-0/+263
|\ | | | | Add remaining UltraPlus cells to ice40 techlib
| * Add remaining UltraPlus cells to ice40 techlibDavid Shah2017-11-281-0/+263
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* | Merge pull request #455 from daveshah1/up5kClifford Wolf2017-11-181-0/+103
|\| | | | | Add UltraPlus specific cells to ice40 techlib
| * Remove unnecessary keep attributesDavid Shah2017-11-181-5/+5
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| * Merge branch 'master' into up5kDavid Shah2017-11-172-5/+29
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| * | Add some UltraPlus cells to ice40 techlibDavid Shah2017-11-161-0/+103
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* | | Merge pull request #453 from dh73/masterClifford Wolf2017-11-1810-5/+312
|\ \ \ | |_|/ |/| | Updating Intel FPGA subsystem with Cyclone 10, minor changes in examples/intel directory and Speedster cells
| * | Initial Cyclone 10 supportdh732017-11-085-1/+308
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| * | Organizing Speedster file namesdh732017-11-085-4/+4
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* / Add "synth_ice40 -vpr"Clifford Wolf2017-11-162-5/+29
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* Clean whitespace and permissions in techlibs/intelLarry Doolittle2017-10-0521-190/+190
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* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-4/+1
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* Tested and working altsyncarm without init filesdh732017-10-012-57/+59
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* Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵dh732017-10-0130-727/+2954
| | | | M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now
* Add first draft of eASIC back-endClifford Wolf2017-09-292-0/+191
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* Fix synth_ice40 doc regarding -top defaultClifford Wolf2017-09-291-1/+1
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* Added RESET_TO_MAX parameter to $__COUNT_ cell. Cannot yet be extracted.Andrew Zonenberg2017-09-142-2/+4
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