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| | * | | | | | intel_synth: Fix help messageBen Widawsky2019-07-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cyclonev has been a "supported" family since the initial commit. The old commit message suggested to use a10gx which is incorrect. Aside from the obvious lack of functional change due to this just being a help message, users who were previously using "a10gx" for "cyclonev" will also have no functional change by using "cyclonev" instead. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| | * | | | | | intel_synth: Small code cleanup to remove if ladderBen Widawsky2019-07-181-28/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| | * | | | | | intel_synth: Make family explicit and matchBen Widawsky2019-07-181-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The help and code default to MAX10 for the family, however the couple of if ladders defaulted to cycloneive. Fix this inconsistency and the next patch will clean it up. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| | * | | | | | intel_synth: Minor code cleanupsBen Widawsky2019-07-181-2/+6
| | | |_|_|_|/ | | |/| | | | | | | | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * / | | | | synth_intel: rename for consistency with #1184Dan Ravensloft2019-07-181-4/+4
| |/ / / / / | | | | | | | | | | | | | | | | | | Also fix a typo in the help message.
| * | | | | Merge pull request #1184 from whitequark/synth-better-labelsClifford Wolf2019-07-185-17/+21
| |\ \ \ \ \ | | | | | | | | | | | | | | synth_{ice40,ecp5}: more sensible pass label naming
| | * | | | | synth_ecp5: rename dram to lutram everywhere.whitequark2019-07-164-13/+13
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| | * | | | | synth_{ice40,ecp5}: more sensible pass label naming.whitequark2019-07-162-5/+9
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| * | | | | Merge pull request #1204 from smunaut/fix_1187David Shah2019-07-172-4/+4
| |\ \ \ \ \ | | | | | | | | | | | | | | ice40: Adapt the relut process passes to the new $lut/SB_LUT4 port map
| | * | | | | ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port mapSylvain Munaut2019-07-162-4/+4
| | | |/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new mapping introduced in 437fec0d88b4a2ad172edf0d1a861a38845f3b1d needed matching adaptation when converting and optimizing LUTs during the relut process Fixes #1187 (Diagnosis of the issue by @daveshah1 on IRC) Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * / | | | gen_lut to return correctly sized LUT maskEddie Hung2019-07-161-1/+1
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| * | | | Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fixEddie Hung2019-07-168-29/+120
| |\ \ \ \ | | |/ / / | |/| | | abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
| | * | | $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequarkEddie Hung2019-07-157-8/+8
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| | * | | ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUTEddie Hung2019-07-131-9/+7
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| | * | | Use Const::from_string() not its constructor...Eddie Hung2019-07-121-1/+1
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| | * | | Off by oneEddie Hung2019-07-121-1/+1
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| | * | | Fix spacingEddie Hung2019-07-121-1/+1
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| | * | | Remove double pushEddie Hung2019-07-121-1/+0
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| | * | | Map to and from this box if -abc9Eddie Hung2019-07-121-2/+3
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| | * | | ice40_opt to handle this box and opt back to SB_LUT4Eddie Hung2019-07-121-0/+48
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| | * | | Add new box to cells_sim.vEddie Hung2019-07-121-2/+25
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| | * | | _ABC macro will map and unmap to this new boxEddie Hung2019-07-122-0/+34
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| | * | | Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 boxEddie Hung2019-07-123-25/+13
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| * | | | Merge pull request #1183 from whitequark/ice40-always-relutClifford Wolf2019-07-121-11/+5
| |\ \ \ \ | | |/ / / | |/| | | synth_ice40: switch -relut to be always on
| | * | | synth_ice40: switch -relut to be always on.whitequark2019-07-111-10/+4
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| | * | | synth_ice40: fix help text typo. NFC.whitequark2019-07-111-1/+1
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| * | | Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
| |\ \ \ | | | | | | | | | | synth_xilinx: Initial Spartan 6 block RAM inference support.
| | * | | synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Kościelnicki2019-07-119-8/+598
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| * / / xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ↵Marcin Kościelnicki2019-07-112-6/+6
| |/ / | | | | | | | | | ISE/Vivado.
* | | Add Tsu offset to boxes, and commentsEddie Hung2019-07-111-6/+11
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* | | ABC doesn't like negative delays in flop boxes...Eddie Hung2019-07-111-6/+6
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* | | Fix FDCE_1 boxEddie Hung2019-07-111-1/+1
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* | | Revert "$pastQ should be first input"Eddie Hung2019-07-111-13/+13
| | | | | | | | | | | | This reverts commit 8f9d529929f43e6ba98f06159ae9533984c6264f.
* | | Propagate INIT attrEddie Hung2019-07-111-5/+5
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* | | $pastQ should be first inputEddie Hung2019-07-111-13/+13
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* | | Fix typoEddie Hung2019-07-111-1/+1
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* | | Simplify to $__ABC_ASYNC boxEddie Hung2019-07-112-19/+8
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* | | $__ABC_FD_ASYNC_MUX.Q -> YEddie Hung2019-07-111-1/+1
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* | | Restore from masterEddie Hung2019-07-101-0/+1
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* | | Another typoEddie Hung2019-07-101-1/+1
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* | | Fix clk_pol for FD*_1Eddie Hung2019-07-101-3/+3
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* | | Another typoEddie Hung2019-07-101-1/+1
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* | | Another typoEddie Hung2019-07-101-1/+1
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* | | Use \$currQEddie Hung2019-07-101-4/+9
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* | | Preserve all parameters, plus some extra ones for clk/en polarityEddie Hung2019-07-101-10/+66
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* | | Change how to specify flops to ABC againEddie Hung2019-07-101-13/+37
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* | | Remove params from FD*_1 variantsEddie Hung2019-07-101-12/+3
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* | | Fix typo, and have !{PRE,CLR} behave as CEEddie Hung2019-07-101-14/+14
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* | | Move ABC FF stuff to abc_ff.v; add support for other FD* typesEddie Hung2019-07-104-27/+135
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* | | Uncomment IS_C_INVERTED parameterEddie Hung2019-07-101-1/+1
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